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HS-RTX2010RH
Data Sheet March 2000 File Number 3961.3
Radiation Hardened Real Time ExpressTM Microcontroller
The HS-RTX2010RH is a radiation-hardened 16-bit microcontroller with on-chip timers, an interrupt controller, a multiply-accumulator, and a barrel shifter. It is particularly well suited for space craft environments where very high speed control tasks which require arithmetically intensive calculations, including floating point math to be performed in hostile space radiation environments. This processor incorporates two 256-word stacks with multitasking capabilities, including configurable stack partitioning and over/underflow control. Instruction execution times of one or two machine cycles are achieved by utilizing a stack oriented, multiple bus architecture. The high performance ASIC Bus, which is unique to the RTX product, provides for extension of the microcontroller architecture using off-chip hardware and application specific I/O devices. RTX Microcontrollers support the C and Forth programming languages. The advantages of this product are further enhanced through third party hardware and software support. Combined, these features make the HS-RTX2010RH an extremely powerful processor serving numerous applications in high performance space systems. The HS-RTX2010RH has been designed for harsh space radiation environments and features outstanding Single Event Upset (SEU) resistance and excellent total dose response. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-95635. A "hot-link" is provided on our homepage for downloading. www.intersil.com/spacedefense/space.asp
Features
* Electrically Screened to SMD # 5962-95635 * QML Qualified per MIL-PRF-38535 Requirements * Fast 125ns Machine Cycle * 1.2M TSOS4 CMOS/SOS Process * Total Dose Capability . . . . . . . . . . . . . . . . . . 300KRad(Si) * Single Event Upset Critical LET . . . . . . . >120MeV/mg/cm2 * Single Event Upset Error Rate . . . . <1 x 10-10 Errors/Bit-Day (Note) * -55oC - 125oC, 5V 10% Operation * Single Cycle Instruction Execution * Fast Arithmetic Operations - Single Cycle 16-Bit Multiply - Single Cycle 16-Bit Multiply Accumulate - Single Cycle 32-Bit Barrel Shift - Hardware Floating Point Support * C Software Development Environment * Direct Execution of Fourth Language * Single Cycle Subroutine Call/Return * Four Cycle Interrupt Latency * On-Chip Interrupt Controller * Three On-Chip 16-Bit Timer/Counters * Two On-Chip 256 Word Stacks * ASIC BusTM for Off-Chip Architecture Extension * 1 Megabyte Total Address Space * Word and Byte Memory Access * Fully Static Design - DC to 8MHz Operation * 84 Lead Quad Flat Package or 85 Pin Grid Array * Third Party Software and Hardware Development Systems
NOTE: Single Event Upset error rates are Adams 10% worst case environment under worst case conditions for upset.
Ordering Information
ORDERING NUMBER 5962F9563501QXC 5962F9563501QYC 5962F9563501V9A 5962F9563501VXC 5962F9563501VYC INTERNAL MKT. NUMBER HS8-RTX2010RH-8 HS9-RTX2010RH-8 HS0-RTX2010RH-Q HS8-RTX2010RH-Q HS9-RTX2010RH-Q TEMP. RANGE (oC) 55 to 125 55 to 125 25 55 to 125 55 to 125 55 to 125 55 to 125
Applications
* Space Systems Embedded Control * Digital Filtering * Image Processing * Scientific Instrumentation * Optical Systems * Control Systems * Attitude/Orbital Control
HS8-RTX2010RH/Proto HS8-RTX2010RH/Proto HS9-RTX2010RH/Proto HS9-RTX2010RH/Proto
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 2000 Real Time ExpressTM, RTXTM, and ASIC BusTM are trademarks of Intersil Corporation.
HS-RTX2010RH Block Diagram
OFF CHIP PERIPHERALS MAIN MEMORY
CONTROL INPUTS
CLOCK AND CONFIGURATION CONTROL
HS-RTX2010RH
ASIC BUS INTERFACE MEMORY BUS INTERFACE
INTERRUPT INPUTS
INTERRUPT CONTROL
MEMORY PAGE CONTROL 256-WORD RETURN STACK
TIMER INPUTS
TIMER/ COUNTERS
RTX CORE PROCESSOR
256-WORD PARAMETER STACK
STACK CONTROLLERS
BARREL SHIFTER MAC
Pinouts
HS8-RTX2010RH MIL-STD-1835 CMGA3-P85C
A B C D E F G H J K L L K J H G F E D C B A 11 MA16 MA19 GND UDS PCLK MD01 MD02 GND MD06 MD07 MD08 10 MD11 MD09 VDD MD05 MD03 NEW BOOT LDS MA18 MA17 MA14 MA14 MA17 MA18 LDS BOOT NEW MD03 MD05 VDD MD09 MD11 9 MD12 MD10 8 MD14 MD13 7 GA00 MD15 GA01 HS-RTX2010RH 6 TCLK GND GA02 5 INTA 4 VDD 3 E I2 NMI E I1 E I4 GD14 GD11 GD10 INTSUP TOP VIEW PINS DOWN MA08 MA07 MA11 MA11 MA07 MA08 MA04 MA05 MA06 MA06 MA05 MA04 MA02 MA03 MA03 MA02 GD01 MA01 MA01 GD01 GD10 GD11 GD14 INTSUP NMI INTA 4 ALIGN. PIN E I1 VDD 3 E I4 E I2 2 GD00 GD02 GD03 GD06 GD08 GD12 GD13 GIO WAIT RESET E I3 1 E I5 A PIN A1 ICLK GR/W GD15 GND GD07 GD09 VDD GD05 GD04 GND B C D E F G H J K L 1 GND GD04 GD05 VDD GD09 GD07 GND GD15 GR/W ICLK E I5 L K J H G F E D C B A PIN A1 MD04 MD00 MR/W MA15 VDD VDD MA13 MA12 GND MA10 MA09 MA09 MA10 GND BOTTOM VIEW PINS UP GA02 GND TCLK 5 GA01 MD15 GA00 6 MA15 MR/W MD00 MD04 MD10 MD12 8 MA12 MA13 MD13 MD14 7 9 10
11 MD08 MD07 MD06 GND MD02 MD01 PCLK UDS GND MA19 MA16
2 E I3 RESET WAIT GIO GD13 GD12 GD08 GD06 GD03 GD02 GD00
NOTE: An overbar on a signal name represents an active LOW signal.
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HS-RTX2010RH Pinouts
(Continued) HS9-RTX2010RH (LEAD LENGTH NOT TO SCALE) SEE INTERSIL OUTLINE R84.A
EI5 EI4 EI3 EI2 EI1 VDD INTSUP NMI INTA TCLK GA02 GA01 GA00 MD15 GND MD14 MD13 MD12 MD11 MD10 MD09 RESET WAIT ICLK GR/W GIO GD15 GD14 GD13 GND GD12 GD11 GD10 GD09 GD08 GD07 VDD GD06 GD05 GD04 GD03 GND 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
HS-RTX2010RH TOP VIEW
MD08 VDD MD07 MD06 MD05 GND MD04 MD03 MD02 MD01 MD00 MR/W PCLK BOOT NEW UDS LDS GND MA19 MA18 MA17
NOTE: An overbar on a signal name represents an active LOW signal.
PGA And CQFP Pin/Signal Assignments
CQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 PGA PIN C6 A6 A5 B5 C5 A4 B4 A3 A2 B3 A1 B2 C2 B1 C1 D2 D1 E3 E2 E1 F2 F3 G3 SIGNAL NAME GA02 TCLK INTA NMI INTSUP VDD EI1 EI2 EI3 EI4 EI5 RESET WAIT ICLK GR/W GIO GD15 GD14 GD13 GND GD12 GD11 GD10 TYPE Output; Address Bus Output Output Input Input Power Input Input Input Input Input Input Input Input Output Output I/O; Data Bus I/O; Data Bus I/O; Data Bus Ground I/O; Data Bus I/O; Data Bus I/O; Data Bus
GD02 GD01 GD00 MA01 MA02 MA03 MA04 MA05 MA06 MA07 MA08 GND MA09 MA10 MA11 MA12 MA13 VDD MA14 MA15 MA16
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
PGA And CQFP Pin/Signal Assignments
CQFP 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 PGA PIN G1 G2 F1 H1 H2 J1 K1 J2 L1 K2 K3 L2 L3 K4 L4 J5 K5 L5 K6 J6 J7 L7 K7 SIGNAL NAME GD09 GD08 GD07 VDD GD06 GD05 GD04 GD03 GND GD02 GD01 GD00 MA01 MA02 MA03 MA04 MA05 MA06 MA07 MA08 GND MA09 MA10
(Continued) TYPE
I/O; Data Bus I/O; Data Bus I/O; Data Bus Power I/O; Data Bus I/O; Data Bus I/O; Data Bus I/O; Data Bus Ground I/O; Data Bus I/O; Data Bus I/O; Data Bus Output; Address Bus Output; Address Bus Output; Address Bus Output; Address Bus Output; Address Bus Output; Address Bus Output; Address Bus Output; Address Bus Ground Output; Address Bus Output; Address Bus
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HS-RTX2010RH PGA And CQFP Pin/Signal Assignments
CQFP 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 PGA PIN L6 L8 K8 L9 L10 K9 L11 K10 J10 K11 J11 H10 H11 F10 G10 G11 G9 F9 F11 SIGNAL NAME MA11 MA12 MA13 VDD MA14 MA15 MA16 MA17 MA18 MA19 GND LDS UDS NEW BOOT PCLK MR/W MD00 MD01
(Continued) TYPE
PGA And CQFP Pin/Signal Assignments
CQFP 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 PGA PIN E11 E10 E9 D11 D10 C11 B11 C10 A11 B10 B9 A10 A9 B8 A8 B6 B7 A7 C7 C3 SIGNAL NAME MD02 MD03 MD04 GND MD05 MD06 MD07 VDD MD08 MD09 MD10 MD11 MD12 MD13 MD14 GND MD15 GA00 GA01 -
(Continued) TYPE
Output; Address Bus Output; Address Bus Output; Address Bus Power Output; Address Bus Output; Address Bus Output; Address Bus Output; Address Bus Output; Address Bus Output; Address Bus Ground Output Output Output Output Output Output I/O; Data Bus I/O; Data Bus
I/O; Data Bus I/O; Data Bus I/O; Data Bus Ground I/O; Data Bus I/O; Data Bus I/O; Data Bus Power I/O; Data Bus I/O; Data Bus I/O; Data Bus I/O; Data Bus I/O; Data Bus I/O; Data Bus I/O; Data Bus Ground I/O; Data Bus Output; Address Bus Output; Address Bus Isolated Alignment Pin
Output Signal Descriptions
SIGNAL OUTPUTS NEW BOOT MR/W UDS LDS GIO GR/W PCLK TCLK INTA 60 61 63 59 58 16 15 62 2 3 1 1 1 1 1 1 1 0 0 0 NEW: A HIGH on this pin indicates that an Instruction Fetch is in progress. BOOT: A HIGH on this pin indicates that Boot Memory is being accessed. This pin can be set or reset by accessing bit 3 of the Configuration Register. MEMORY READ/WRITE: A LOW on this pin indicates that a Memory Write operation is in progress. UPPER DATA SELECT: A HIGH on this pin indicates that the high byte of memory (MD15-MD08) is being accessed. LOWER DATA SELECT: A HIGH on this pin indicates that the low byte of memory (MD07-MD00) is being accessed. ASIC I/O: A LOW on this pin indicates that an ASIC Bus operation is in progress. ASIC READ/WRITE: A LOW on this pin indicates that an ASIC Bus Write operation is in progress. PROCESSOR CLOCK: Runs at half the frequency of ICLK. All processor cycles begin on the rising edge of PCLK. Held low extra cycles when WAIT is asserted. TIMING CLOCK: Same frequency and phase as PCLK but continues running during Wait cycles. INTERRUPT ACKNOWLEDGE: A HIGH on this pin indicates that an Interrupt Acknowledge cycle is in progress. CQFP RESET LEVEL DESCRIPTION
Input Signal, Bus, and Power Connection Descriptions
SIGNAL INPUTS WAIT ICLK RESET 13 14 12 WAIT: A HIGH on this pin causes PCLK to be held LOW and the current cycle to be extended. INPUT CLOCK: Internally divided by 2 to generate all on-chip timing (CMOS input levels). A HIGH level on this pin resets the RTX. Must be held high for at least 4 rising edges of ICLK plus 12 ICLK cycle setup and hold times. CQFP LEAD DESCRIPTION
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HS-RTX2010RH Input Signal, Bus, and Power Connection Descriptions
SIGNAL EI2, EI1 EI5-EI3 CQFP LEAD 8, 7 11-9 (Continued)
DESCRIPTION EXTERNAL INTERRUPTS 2, 1: Active HIGH level-sensitive inputs to the Interrupt Controller. Sampled on the rising edge of PCLK. See Timing Diagrams for detail. EXTERNAL INTERRUPTS 5, 4, 3: Dual purpose inputs; active HIGH level-sensitive Interrupt Controller inputs; active HIGH edge-sensitive Timer/Counter inputs. As interrupt inputs, they are sampled on the rising edge of PCLK. See Timing Diagrams for detail. NON-MASKABLE INTERRUPT: Active HIGH edge-sensitive Interrupt Controller input capable of interrupting any processor cycle when NMI is set to Mode 0. See the Interrupt Suppression and Interrupt Controller Sections. INTERRUPT SUPPRESS: A HIGH on this pin inhibits all maskable interrupts, internal and external.
NMI INTSUP
4 5
ADDRESS BUSES (OUTPUTS) GA02 GA01 GA00 MA19-MA14 MA13-MA09 MA08-MA01 DATA BUSES (I/O) GD15-GD13 GD12-GD07 GD06-GD03 GD02-GD00 MD15 MD14-MD08 MD07-MD05 MD04-MD00 17-19 21-26 28-31 33-35 82 80-74 72-70 68-64 MEMORY DATA: 16-bit bidirectional Memory Data Bus, which carries data to and from Main Memory. ASIC DATA: 16-bit bidirectional external ASIC Data Bus, which carries data to and from off-chip I/O devices. 1 84 83 56-51 49-45 43-36 MEMORY ADDRESS: 19-bit Memory Address Bus, which carries address information for Main Memory. ASIC ADDRESS: 3-bit ASIC Address Bus, which carries address information for external ASIC devices.
POWER CONNECTIONS VDD GND 6, 27, 50, 73 20, 32, 44, 57, 69, 81 Power supply +5V connections. A 0.1F, low impedance decoupling capacitor should be placed between VDD and GND. This should be located as close to the RTX package as possible. Power supply ground return connections.
TYPICAL CLOCK OR STROBE
tPULSE WIDTH 4.0V 0.5V tSETUP 2.25V
tPULSE WIDTH 2.25V tHOLD 2.25V
TYPICAL INPUT
4.0V 0.5V tDELAY 2.25V 2.25V tDELAY
TYPICAL OUTPUT tVALID TYPICAL DATA OUTPUT
2.25V tHOLD
2.25V
2.75V 1.75V
2.75V 1.75V
FIGURE 1. AC DRIVE AND MEASURE POINTS - CLK INPUT
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HS-RTX2010RH Timing Diagrams
t1 t2 ICLK t11 TCLK t13 WAIT t15 PCLK (NOTE 1) PCLK (NOTE 2) GIO (NOTE 3) t51 t20 t5 t12 t5 t4 t4 t19 t3
t17
t16
t20 t50
NOTES: 1. NORMAL CYCLE: This waveform describes a normal PCLK cycle and a PCLK cycle with a Wait state. 2. EXTENDED CYCLE: This waveform describes a PCLK cycle for a USER memory access or an external ASIC Bus read cycle when the CYCEXT bit or ARCE bit is set. 3. EXTENDED CYCLE: This waveform describes a GIO cycle for an external ASIC Bus read when the ARCE bit is set. 4. An active HIGH signal on the RESET input is guaranteed to reset the processor if its duration is greater than or equal to 4 rising edges of ICLK plus 1/2 ICLK cycle setup and hold times. If the RESET input is active for less than four rising edges of ICLK, the processor will not reset. FIGURE 2. CLOCK AND WAIT TIMING
t6 EI5 - EI3 t7 t8
FIGURE 3. TIMER/COUNTER TIMING
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HS-RTX2010RH Timing Diagrams
PCLK t26 MA LDS UDS NEW BOOT MR/W MD IN t32 t34 MD OUT t33 t35 t29 t31 t28
(Continued)
t21 t22
NOTES: 5. If both LDS and UDS are low, no memory access is taking place in the current cycle. This only occurs during streamed instructions that do not access memory. 6. During a streamed single cycle instruction, the Memory Data Bus is driven by the processor. FIGURE 4. MEMORY BUS TIMING
ICLK t50 GIO t48 PCLK t52 GA t56 GR/W t40A, B t41A, B t62 GD OUT t61 t63 t43 t42 t65 t58 t54 t49 t69 t51
GD IN
NOTES: 7. GIO remains high for internal ASIC bus cycles. 8. GR/W goes low and GD is driven for all ASIC write cycles, including internal ones. 9. During non-ASIC write cycles, GD is not driven by the HS-RTX2010RH. Therefore, it is recommended that all GD pins be pulled to VCC or GND to minimize power supply current and noise. 10. t40B and t41B specifications are for Streamed Mode of operation only. FIGURE 5. ASIC BUS TIMING
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HS-RTX2010RH Timing Diagrams
(Continued)
e1 PCLK t44 EI t46 t47 t46 t47 e2 e3 e4 e5
INTSUP t67 INTA t26 MA INT VECTOR t28 t68
NOTES: 11. Events in an interrupt sequence are as follows: e1. The Interrupt Controller samples the interrupt request inputs on the rising edge of PCLK. If NMI rises between e1 and the rising edge of PCLK prior to e5, the interrupt vector will be for NMI. e2. If any interrupt requests were sampled, the Interrupt Controller issues an interrupt request to the core on the falling edge of PCLK. e3. The core samples the state of the interrupt requests from the Interrupt Controller on the falling edge of PCLK. If INTSUP is high, maskable interrupts will not be detected at this time. e4. When the core samples an interrupt request on the falling edge of PCLK, an Interrupt Acknowledge cycle will begin on the next rising edge of PCLK. e5. Following the detection of an interrupt request by the core, an Interrupt Acknowledge cycle begins. The interrupt vector will be based on the highest priority interrupt request active at this time. 12. t44 is only required to determine when the Interrupt Acknowledge cycle will occur. 13. Interrupt requests should be held active until the Interrupt Acknowledge cycle for that interrupt occurs. FIGURE 6. INTERRUPT TIMING: WITH INTERRUPT SUPPRESSION
e1 PCLK t44 EI
e2
e4
e5
t46
t47
INTSUP t67 INTA t26 MA INT VECTOR t28 t68
FIGURE 7. INTERRUPT TIMING: WITH NO INTERRUPT SUPPRESSION
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HS-RTX2010RH Timing Diagrams
(Continued)
e1 PCLK t44 NMI t67 INTA t26 MA NMI VECTOR t28 t68 e2 e4 e5
NOTES: 14. Events in an interrupt sequence are as follows: e1. The Interrupt Controller samples the interrupt request inputs on the rising edge of PCLK. If NMI rises between e1 and the rising edge of PCLK prior to e5, the interrupt vector will be for NMI. e2. If any interrupt requests were sampled, the Interrupt Controller issues an interrupt request to the core on the falling edge of PCLK. e4. When the core samples an interrupt request on the falling edge of PCLK, an Interrupt Acknowledge cycle will begin on the next rising edge of PCLK. e5. Following the detection of an interrupt request by the core, an Interrupt Acknowledge cycle begins. The interrupt vector will be based on the highest priority interrupt request active at this time. 15. t44 is only required to determine when the Interrupt Acknowledge cycle will occur. 16. Interrupt requests should be held active until the Interrupt Acknowledge cycle for that interrupt occurs. 17. NMI has a glitch filter which requires the signal that initiates NMI last at least two rising and two falling edges of ICLK. FIGURE 8. NON-MASKABLE INTERRUPT TIMING
HS-RTX2010RH Microcontroller
The HS-RTX2010RH is designed around the RTX Processor core, which is part of the Intersil Standard Cell Library. This processor core has eight 16-bit internal registers, an ALU, internal data buses, and control hardware to perform instruction decoding and sequencing. On-chip peripherals which the HS-RTX2010RH includes are Memory Page Controller, an Interrupt Controller, three Timer/Counters, and two Stack Controllers. Also included are a Multiplier-Accumulator (MAC), a Barrel Shifter, and a Leading Zero Detector for floating point support. Off-chip user interfaces provide address and data access to Main Memory and ASIC I/O devices, user defined interrupt signals, and Clock/Reset controls. Figure 9 shows the data paths between the core, on-chip peripherals, and off-chip interfaces. The HS-RTX2010RH microcontroller is based on a two-stack architecture. These two stacks, which are Last-In-First-Out (LIFO) memories, are called the Parameter Stack and the Return Stack. Two internal registers, TOP and NEXT , provide the top two elements of the 16-bit wide Parameter Stack, while the remaining elements are contained in on-chip memory ("stack memory"). The top element of the Return Stack is 21 bits wide, and is stored in registers I and IPR , while the remaining elements are contained in stack memory. The highly parallel architecture of the RTX is optimized for minimal Subroutine Call/Return overhead. As a result, a Subroutine Call takes one Cycle, while a Subroutine Return is usually incorporated into the preceding instruction and does not add any processor cycles. This parallelism provides for peak execution rates during simultaneous bus operations which can reach the equivalent of 32 million Forth language operations per second at a clock rate of 8MHz. Typical execution rates exceed 8 million operations per second. Intersil factory applications support for this device is limited. RTS-C C-Compiler support is provided by Highland Software at highlandsoft@compuserve.com. Development system tools are supported by Micro Processor Engineering Limited (UK) at 441 703 631441. A HS-RTX2010RH programmers reference manual can be obtained through your local Intersil Sales Office.
9
HS-RTX2010RH
INTSUP NMI INTA EI2-EI1 EI5-EI3 MEMORY PAGE CONTROL IPR DPR UPR CPR UBR STACK CONTROL SPR SVR SUR INTERRUPT CONTROL IMR IVR IBC TIMER/COUNTERS TC0 TC1 TC2 TP0 TP1 TP2 16 x 16 MAC MXR 256 x 21 RETURN STACK MEMORY INSTRUCTION DECODER 256 x 16 PARAMETER STACK MEMORY YT ALU MHR MLR OFF-CHIP USER INTERFACES ICLK WAIT PCLK TCLK RESET CLOCK AND RESET CONTROL MA19MA01 UDS LDS NEW BOOT MR/W MD15MD00 GA2GA0 GD15GD00 (NOTE) BYTE SWAP GR/W
HS-RTX2010RH
MEMORY BUS INTERFACE
ASIC BUS INTERFACE
GIO
-1
I
+1 PC IR NEXT CR MD SR TOP
BARREL SHIFTER LEADING ZERO DETECTOR
NOTE:
IPR contains the 5 most significant bits (20-16) of the top element of the Return Stack.
FIGURE 9. HS-RTX2010RH FUNCTIONAL BLOCK DIAGRAM
HS-RTX2010RH Operation
Control of all data paths and the Program Counter Register, ( PC ), is provided by the Instruction Decoder. This hardware determines what function is to be performed by looking at the contents of the Instruction Register, ( IR ), and subsequently determines the sequence of operations through data path control. Instructions which do not perform memory accesses execute in a single clock cycle while the next instruction is being fetched. As shown in Figure 10, the instruction is latched into IR at the beginning of a clock cycle. The instruction is then decoded by the processor. All necessary internal operations are performed simultaneously with fetching the next instruction. Instructions which access memory require two clock cycles to be executed. During the first cycle of a memory access instruction, the instruction is decoded, the address of the memory location to be accessed is placed on the Memory Address Bus (MA19-MA01), and the memory data (MD15-MD00), is read or written. During the second cycle, ALU operations are performed, the address of the next instruction to be executed is placed on the Memory Address Bus, and the next instruction is fetched, as indicated in the bottom half of Figure 10.
10
HS-RTX2010RH
PCLK EXECUTION SEQUENCE WITH NO MEMORY DATA ACCESS: BEGIN FIRST CLOCK CYCLE END OF FIRST CLOCK CYCLE BEGIN SECOND CLOCK CYCLE
CONCURRENT OPERATIONS
PERFORM INTERNAL OPERATIONS AND ALU OPERATIONS, AS REQUIRED ADDRESS OF NEXT INSTRUCTION IS PLACED ONTO MA19-MA01 BUS
DECODE
INSTRUCTION LATCHES INTO IR
FETCH
ASIC BUS OPERATIONS
EXECUTION SEQUENCE WITH MEMORY DATA ACCESS: BEGIN FIRST CLOCK CYCLE END OF FIRST CLOCK CYCLE BEGIN SECOND CLOCK CYCLE END OF SECOND CLOCK CYCLE
CONCURRENT OPERATIONS PERFORM ALU OPERATIONS
DECODE
INSTRUCTION LATCHES INTO IR
ADDRESS OF MEMORY LOCATION IS PLACED ONTO MA19-MA01 BUS
READ OR WRITE MEMORY DATA
PLACE ADDRESS OF NEXT INSTRUCTION ONTO MA19-MA01
FETCH NEXT INSTRUCTION
FIGURE 10. INSTRUCTION EXECUTION SEQUENCE
RTX Data Buses and Address Buses
The RTX core bus architecture provides for unidirectional data paths and simultaneous operation of some data buses. This parallelism allows for maximum efficiency of data flow internal to the core. Addresses for accessing external (off-chip) memory or ASIC devices are output via either the Memory Data Bus (MA19-MA01) or the ASIC Address Bus (GA02-GA00). See Table 3. External data is transferred by the ASIC Data Bus (GD15-GD00) and the Memory Data Bus (MD15-MD00), both of which are bidirectional.
also holds the most significant 16 bits of 32-bit products and 32-bit dividends. NEXT: The Next Register holds the second element of the Parameter Stack. EXT is the implicit data source or destination for certain instructions, and has no ASIC address assignment. During a stack "push", the contents of NEXT are transferred to stack memory, and the contents of TOP are put into NEXT. This register is used to hold the least significant 16 bits of 32-bit products. Memory data is accessed through NEXT, as described in the Memory Access section of this document. IR : The Instruction Register is actually a latch which contains the instruction currently being executed, and has no ASIC address assignment. In certain instructions, an operand can be embedded in the instruction code, making IR the implicit source for that operand (as in the case of short literals). Input to this register comes from Main Memory (see Tables 6 thru 22 for code information). CR : The Configuration Register is used to indicate and control the current status/setup of the RTX microcontroller, through the bit assignments shown in Figure 11. This register is accessed explicitly through read and write operations, which cause interrupts to be suppressed for one cycle, guaranteeing that the next instruction will be performed before an Interrupt Acknowledge cycle is allowed to be performed.
RTX Internal Registers
The core of the HS-RTX2010RH is a macrocell available through the Intersil Standard Cell Library. This core contains eight 16-bit internal registers, which may be accessed implicitly or explicitly, depending upon the register accessed and the function being performed. TOP : The Top Register contains the top element of the Parameter Stack++. TOP is the implicit data source or destination for certain instructions, and has no ASIC address assignment. The contents of this register may be directed to any I/O device or to any processor register except the Instruction Register. TOP is also the T input to the ALU. Input to TOP must come through the ALU. This register
11
HS-RTX2010RH
CR 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 1 R/W; CARRY R/W; COMPLEX CARRY R/W; BYTE ORDER BIT RESETS TO 0. MODES: 1 = ADDRESSING MODE 1 0 = ADDRESSING MODE 0 R/W; BOOT DRIVES OUTPUT SIGNAL TO SELECT BOOT ROM; WRITE - ONLY (READS AS 0); SET INTERRUPT DISABLE; 0 = INT. ENABLED; 1 = INT. DISABLED RESERVED (NOTE) NMI MODE 1 = RETURN FROM NMI POSSIBLE 0 = NO RETURN FROM NMI (RTX 2000 MODE) RESERVED (NOTE) ARCE; ASIC READ CYCLE EXTEND WHEN SET EXTENDS CYCLE ON EXTERNAL ASIC READS READ ONLY; INTERRUPT DISABLE STATUS READ ONLY; INTERRUPT LATCH
Timer/Counter Registers
TC0 , TC1 , TC2 : The Timer/Counter Registers are 16-bit read-only registers which contain the current count value for each of the three Timer/Counters. The counter is decremented at each rising clock edge of TCLK. Reading from these registers at any time does not disturb their contents. The sequence of Timer/Counter operations is shown in Figure 23 in the Timer/Counters section. TP0 , TP1 , TP2 : The Timer Preload Registers are write-only registers which contain the initial 16-bit count values which are written to each timer. After a timer counts down to zero, the preload register for that timer reloads its initial count value to that timer register at the next rising clock edge, synchronously with TCLK. Writing to these registers causes the count to be loaded into the corresponding Timer/ Counter register on the following cycle.
Multiplier-Accumulator (MAC) Registers:
MHR : The Multiplier High Product Register holds the most significant 16 bits of the 32-bit product generated by the RTX Multiplier. If the IBC register's ROUND bit is set, this register contains the rounded 16-bit output of the multiplier. In the Accumulator context, this register holds the middle 16 bits of the MAC. MLR : The Multiplier Lower Product Register holds the least significant 16 bits of the 32-bit product generated by the RTX Multiplier. It is also the register which holds the least significant 16 bits of the MAC Accumulator. MXR : The MAC Extension Register holds the most significant 16 bits of the MAC Accumulator. When using the Barrel Shifter, this register holds the shift count. When using the Leading Zero Detector, the leading zero count is stored in this register.
NOTE: Always read as ``0''. Should be set = 0 during Write operations. FIGURE 11.
CR BIT ASSIGNMENTS
PC : The Program Counter Register contains the address of the next instruction to be fetched from Main Memory. At RESET, the contents of PC are set to 0. I : The Index Register contains 16 bits of the 21-bit top element of the Return Stack, and is also used to hold the count for streamed and loop instructions (see Figure 19). In addition, I can be used to hold data and can be written from TOP . The contents of I may be accessed in either the push/pop mode in which values are moved to/from stack memory as required, or in the read/write mode in which the stack memory is not affected. The ASIC address used for I determines what type of operation will be performed (see Table 5). When the Streamed Instruction Mode (see RTX Programmer's Reference Manual) is used, a count is written to I and the next instruction is executed that number of times plus one (i.e., count + 1). MD : The Multi-Step Divide Register holds the divisor during Step Divide operations, while the 32-bit dividend is in TOP and EXT. MD may also be used as a general purpose scratch pad register. SR : The Square Root Register holds the intermediate values used during Step Square Root calculations. SR may also be used as a general purpose scratch pad register.
Interrupt Controller Registers
IVR : The Interrupt Vector Register is a read-only register which holds the current Interrupt Vector value. See Figure 12 and Table 4.
IBC BIT 15 IBC BIT 14 IBC BIT 13 IBC BIT 12 IBC BIT 11 IBC BIT 10 VECTOR ADDRESS (SEE TABLE 1) ALL ZEROS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 IBC 10 MA15-MA00
IVR
On-Chip Peripheral Registers
The HS-RTX2010RH has an on-chip Interrupt Controller, a Memory Page Controller, two Stack Controllers, three Timer/Counters, a Multiplier-Accumulator, a Barrel Shifter, and a Leading Zero Detector. Each of these peripherals utilizes on-chip registers to perform its functions. 12
FIGURE 12.
IVR BIT ASSIGNMENTS
IBC : The Interrupt Base/Control Register is used to store the Interrupt Vector base address and to specify configuration information for the processor, as indicated by the bit assignments in Figure 13.
HS-RTX2010RH
PARAMETER STACK FATAL ERROR RETURN STACK FATAL ERROR SUR SVR IBC 1514 13 12 1110 9 8 7 6 5 4 3 2 1 0 READ-ONLY; FATAL STACK ERROR FLAG READ-ONLY; PARAMETER STACK UNDERFLOW FLAG READ-ONLY; RETURN STACK UNDERFLOW FLAG READ-ONLY; PARAMETER STACK OVERFLOW FLAG READ-ONLY; RETURN STACK OVERFLOW FLAG DPRSEL: SELECTS PAGE REGISTER FOR DATA MEMORY ACCESS = 1: SELECT DPR = 0: SELECT CPR ROUND: MULTIPLIER CONTROL BIT; SELECTS ROUNDING OF 16 x 16 BIT MULTIPLICATION = 1: ROUNDED 16-BIT PRODUCT = 0: UNROUNDED 32-BIT PRODUCT CYCEXT: ALLOWS EXTENDED CYCLE LENGTH FOR USER MEMORY INSTRUCTION CYCLES; SEE CLOCK AND WAIT TIMING DIAGRAMS SELECT TIMER/COUNTER INPUT SIGNALS: TCLK OR EI5 - EI3 (TABLE 6) IMR 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 RESERVED (NOTE) EI1 (EXTERNAL INPUT PIN) PSU, PARAMETER STACK UNDERFLOW RSU, RETURN STACK UNDERFLOW PSV, PARAMETER STACK OVERFLOW RSV, RETURN STACK OVERFLOW EI2 TCI 0 TCI 1 TCI 2 EI3 EI4 EI5 SWI RESERVED (NOTE)
NOTE: Always read as ``0''. Should be set = 0 during Write operations. FIGURE 14. IMR BIT ASSIGNMENTS
Stack Controller Registers
SPR : The Stack Pointer Register holds the stack pointer value for each stack. Bits 0-7 represent the next available stack memory location for the Parameter Stack, while bits 815 represent the next available stack memory location for the Return Stack. These stack pointer values must be accessed together, as SPR . See Figure 15. SVR : The Stack Overflow Limit Register is a write-only register which holds the overflow limit values (0 to 255) for the Parameter Stack (bits 0-7) and the Return Stack (bits 8-15). These values must be written together. See Figure 16. SUR : The Stack Underflow Limit Register holds the underflow limit values for the Parameter Stack and the Return Stack. In addition, this register is utilized to define the use of substacks for both stacks. These values must be accessed together. See Figure 17.
SPR 15 14 1312 1110 9 8 7 6 5 4 3 2 1 0 PSP, PARAMETER STACK POINTER RSP, RETURN STACK POINTER
INTERRUPT VECTOR BASE (SEE THE INTERRUPT SECTION)
MA15 MA14 MA13 MA12 MA11 MA10
FIGURE 13.
IBC BIT ASSIGNMENTS
IMR : The Interrupt Mask Register has a bit assigned for each maskable interrupt which can occur. When a bit is set, the interrupt corresponding to that bit will be masked. Only the Non-Maskable Interrupt (NMI) cannot be masked. See Figure 14 for bit assignments for this register.
FIGURE 15. SPR BIT ASSIGNMENTS
SVR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PVL: PARAMETER STACK OVERFLOW LIMIT. NUMBER OF WORDS FROM TOP OF CURRENT SUBSTACK RVL: RETURN STACK OVERFLOW LIMIT. NUMBER OF WORDS FROM TOP OF CURRENT SUBSTACK
FIGURE 16. SVR BIT ASSIGNMENTS
13
HS-RTX2010RH
SUR 1 14 13 12 1 110 9 8 7 6 5 4 3 2 1 0 5 PSF: PARAMETER STACK START FLAG PARAMETER SUBSTACK BITS: = 00: EIGHT 32 WORD STACKS = 01: FOUR 64 WORD STACKS = 10: TWO 128 WORD STACKS = 11: ONE 256 WORD STACK PSU: PARAMETER STACK UNDERFLOW LIMIT 0 - 31 WORDS FROM BOTTOM OF SUBSTACK RSF: RETURN STACK START FLAG RETURN SUBSTACK BITS: = 00: EIGHT 32 WORD STACKS = 01: FOUR 64 WORD STACKS = 10: TWO 128 WORD STACKS = 11: ONE 256 WORD STACK RSU: RETURN STACK UNDERFLOW LIMIT 0 - 31 WORDS FROM BOTTOM OF SUBSTACK BIT ASSIGNMENTS DURING SUBROUTINE OPERATIONS IPR I
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TYPE OF RETURN = 1: INTERRUPT RETURNS: = 0: SUBROUTINE RETURNS: DEFINES RETURN ADDRESS WHERE DPRSEL BIT IS STORED DURING INTERRUPT OR SUBROUTINE CALL BIT ASSIGNMENTS DURING NON-SUBROUTINE OPERATIONS IPR I
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USED FOR TEMPORARY STORAGE OF VARIABLES, LOOP COUNTS, AND STREAM COUNTS CURRENT CODE PAGE VALUE
FIGURE 17. SUR BIT ASSIGNMENTS
FIGURE 19.
I AND IPR BIT ASSIGNMENTS
DPR
Memory Page Controller Registers
CPR : The Code Page Register contains the value for the current 32K-word Code page. See Figure 18 for bit field assignments.
CPR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 RESERVED (NOTE) MA19 MA18 MA17 MA16 10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 RESERVED (NOTE) MA19 MA18 MA17 MA16 10
NOTE: Always read as ``0''. Should be set = 0 during Write operations. FIGURE 20. DPR BIT ASSIGNMENTS
USER PAGE REGISTER RESERVED (NOTE) MA19 MA18 MA17 MA16 USER BASE ADDRESS REGISTER MA15 - MA06 MA05 MA04 MA03 MA02 MA01 NOT USED TO GENERATE THIS ADDRESS INSTRUCTION REGISTER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 IR 10 RESERVED (NOTE) UBR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 10
UPR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 10
NOTE: Always read as ``0''. Should be set = 0 during Write operations. FIGURE 18. CPR BIT ASSIGNMENTS
IPR : The Index Page Register extends the Index Register ( I ) by 5 bits; i.e., when a Subroutine Return is performed, the IPR contains the Code page from which the subroutine was called, and comprises the 5 most significant bits of the top element of the Return Stack. See Figure 19. During nonsubroutine operation, writing to I causes the current Code page value to be written to IPR . Reading or writing directly to IPR does not push the Return Stack. DPR : The Data Page Register contains the value for the current 32K-word Data page. See Figure 20 for bit field assignments. UPR : The User Page Register contains the value for the current User page. See Figure 21 for bit field assignments. UBR : The User Base Address Register contains the base address for User Memory Instructions. See Figure 21 for bit field assignments.
NOTE: Always read as ``0''. Should be set = 0 during Write operations. FIGURE 21. UPR AND UBR BIT ASSIGNMENTS
14
HS-RTX2010RH Initialization of Registers
Initialization of the on-chip registers occurs when a HIGH level on the RTX RESET pin is held for a period of greater than or equal to four rising edges of ICLK plus 1/2 ICLK cycle setup and hold times. While the RESET input is HIGH, the TCLK and PCLK clock outputs are held reset in the LOW state. Table 1 shows initialization values and ASIC addresses for the on-chip registers. As indicated, both the PC and the CPR are cleared and execution begins at page 0, word 0 when the processor is reset. The RESET has a Schmitt trigger input, which allows the use of a simple RC network for generation of a power-on RESET signal. This helps to minimize the circuit board space required for the RESET circuit. To ensure reliable operation even in noisy embedded control environments, the RESET input is filtered to prevent a reset caused by a glitch of less than four ICLK cycles duration.
TABLE 1. REGISTER INITIALIZATION AND ASIC ADDRESS ASSIGNMENTS REGISTER HEX ADDR INITIALIZED CONTENTS 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 00H 01H 02H 03H 04H 06H 07H 08H 09H 0AH 0BH 1111 1111 1111 1111 Top Register Next Register Instruction Register Index Register DESCRIPTION/COMMENTS
TOP NEXT IR I CR MD SR PC IMR SPR SUR IVR SVR IPR DPR UPR CPR IBC UBR MXR TC0 / TP0 TC1 / TP1 TC2 / TP2 MLR MHR
0100 0000 0000 1000 1111 1111 1111 1111 0000 0010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0111 0000 0111 0000 0010 0000 0000
Configuration Register: Boot = 1; Interrupts Disabled; Byte Order = 0. Multi-Step Divide Register Square Root Register Program Counter Register Interrupt Mask Register Stack Pointer Register: The beginning address for each stack is set to a value of `0'. Stack Underflow Limit Register Interrupt Vector Register: Read only; this register holds the current Interrupt Vector value, and is initialized to the "No Interrupt" value. Stack Overflow Limit Register: Write-only; Each stack limit is set to its maximum value. Index Page Register Data Page Register: The Data Address Page is set for page `0'. User Page Register: The User Address Page is set for page `0'. Code Page Register: The Code Address Page is set for page `0'. Interrupt Base/Control Register User Base Address Register: The User base address is set to `0' within the User page. MAC Extension Register Timer/Counter Register 0: Set to time out after 65536 clock periods or events. Timer/Counter Register 1: Set to time out after 65536 clock periods or events. Timer/Counter Register 2: Set to time out after 65536 clock periods or events. Multiplier Lower Product Register Multiplier High Product Register
0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H
1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
15
HS-RTX2010RH Dual Stack Architecture
The HS-RTX2010RH features a dual stack architecture. The two 256-word stacks are the Parameter Stack and the Return Stack, both of which may be accessed in parallel by a single instruction, and which minimize overhead in passing parameters between subroutines. The functional structure of each of these stacks is shown in Figure 22. The Parameter Stack is used for temporary storage of data and for passing parameters between subroutines. The top two elements of this stack are contained in the TOP and NEXT registers of the processor, and the remainder of this stack is located in stack memory. The stack memory assigned to the Parameter Stack is 256 words deep by 16 bits wide. The Return Stack is used for storing return addresses when performing Subroutine Calls, or for storing values temporarily. Because the HS-RTX2010RH uses a separate Return Stack, it can call and return from subroutines and interrupts with a minimum of overhead. The Return Stack is 21 bits wide. The 16-bit Index Register, I , and the 5-bit Index Page Register, IPR , hold the top element of this stack, while the remaining elements are located in stack memory. The stack memory portion of the Return Stack is 21 bits wide, by 256 words deep. The data on the Return Stack takes on different meaning, depending upon whether the Return Stack is being used for temporary storage of data or to hold a return address during a subroutine operation (Figure 19).
HS-RTX2010RH Stack Controllers
The two stacks of the HS-RTX2010RH are controlled by identical Programmable Stack Controllers. The operation of the Programmable Stack Controllers depends on the contents of three registers. These registers are SPR , the Stack Pointer Register, SVR , the Stack Overflow Limit Register, and SUR , the Stack Underflow Limit Register (see Figures 15, 16, and 17). SPR contains the address of the next stack memory location to be accessed in a stack push (write) operation. After a push, the SPR is incremented (post-increment operation). In a stack pop (read) operation, the stack memory location with an address one less than the SPR will be accessed, and then the SPR will be decremented (pre-decrement operation). At start-up, the first stack location to have data pushed into it is location zero. Upper and lower limit values for the stacks are set into the Stack Overflow Limit Register and in the Stack Underflow Limit Register. These values allow interrupts to be generated prior to the occurrence of stack overflow or underflow error conditions (see section on Stack Error Conditions for more detail). Since the HS-RTX2010RH can take up to four clock cycles to respond to an interrupt, the values set in these registers should include a safety margin which allows valid stack operation until the processor executes the interrupt service routine.
SPR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PARAMETER STACK TOP 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 NEXT 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 PSU PSP RSP STACK MEMORY (ON-CHIP) STACK MEMORY (ON-CHIP)
RETURN STACK IPR I 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSU
RVL
PVL
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SVR
FIGURE 22. DUAL STACK ARCHITECTURE
16
HS-RTX2010RH
Substacks
Each 256-word stack may be subdivided into up to eight 32 word substacks, four 64 word substacks, or two 128 word substacks. This is accomplished under hardware control for simplified management of multiple tasks. Stack size is selected by writing to bits 1 and 2 of the SUR for the Parameter Stack, and bits 9 and 10 for the Return Stack. Substacks are implemented by making bits 5-7 of the SPR (for the Parameter Stack) and bits 13-15 of the SPR (for the Return Stack) control bits. For example, if there were eight 32 word substacks implemented in the Parameter Stack, bits 5-7 of the SPR are not incremented, but instead are used as an offset pointer into the Parameter Stack to indicate the beginning point (i.e., sub stack number) of each 32 word substack implemented. Because of this, a particular substack is selected by writing a value which contains both the stack pointer value and the substack number to the SPR . Each stack has a Stack Start Flag (PSF and RSF) which may be used for implementing virtual stacks. For the Parameter Stack, the Start Flag is bit zero of the SUR , and for the Return Stack it is bit eight. If the Stack Start Flag is one, the stack starts at the bottom of the stack or substack (location 0). If the Stack Start Flag is zero, the substack starts in the middle of the stack. An exception to this occurs if the overflow limit in SVR is set for a location below the middle of the stack. In this case, the stacks always start at the bottom locations. See Table 2 for the possible stack configurations. Manipulating the Stack Start Flag provides a mechanism for creating a virtual stack in memory which is maintained by interrupt driven handlers. Possible applications for substacks include use as a recirculating buffer (to allow quick access for a series of repeated values such as coefficients for polynomial evaluation or a digital filter), or to log a continuous stream of data until a triggering event (for analysis of data before and after the trigger without having to store all of the incoming data). The latter application could be used in a digital oscilloscope or logic analyzer. read but not written to. All stack error flags are cleared whenever a new value is written to SPR . Fatal Stack Error: Each stack can also experience a fatal stack error. This error condition occurs when an attempt is made to push data onto or to pop data off of the highest location of the substack. It does not generate an interrupt (since the normal stack limits can be used to generate the interrupt). The fatal errors for the stacks are logically OR'ed together to produce bit 0 of the Interrupt Base Control Register, and they are cleared whenever SPR is written to. The implication of a fatal error is that data on the stack may have been corrupted or that invalid data may have been read from the stack.
HS-RTX2010RH Timer/Counters
The HS-RTX2010RH has three 16-bit timers, each of which can be configured to perform timing or event counting. All decrement synchronously with the rising edge of TCLK. Timer registers are readable in a single machine cycle. The timer selection bits of the IBC determine whether a timer is to be configured for external event counting or internal time-base timing. This configures the respective counter clock inputs to the on-chip TCLK signal for internal timing, or to the EI5 - EI3 input pins for external signal event counting. EI5, EI4, and EI3 are synchronized internally with TCLK. See Table 3 for Timer/Clock selection by IBC bit values. The timers ( TC0 , TC1 and TC2 ) are all free-running, and when they time out, they reload automatically with the programmed initial value from their respective Timer Pre load Registers ( TPO TC0 , TP1 TC1 , and TP2 TC2 ), then continue timing or counting. Each timer provides an output to the Interrupt Controller to indicate when a time-out for the timer has occurred. The HS-RTX2010RH can determine the state of a timer at any time either by reading the timer's value, or upon a timeout by using the timer's interrupt (see the Interrupt Controller section for more information about how timer interrupts are handled). Figure 23 shows the sequence of Timer/Counter operations.
Stack Error Conditions
Stack errors include overflow, underflow, and fatal errors. Overflows occur when an attempt is made to push data onto a full stack. Since the stacks wrap around, the result is that existing data on the stack will be overwritten by the new data when an overflow occurs. Underflows occur when an attempt is made to pop data off an empty stack, causing invalid data to be read from the stack. In both cases, a buffer zone may be set up by initializing SVR and SUR so that stack error interrupts are generated prior to an actual overflow or underflow. The limits may be determined from the contents of SVR and SUR using Table 2. The state of all stack errors may be determined by examining the five least significant bits of IBC , where the stack error flags may be
17
TABLE 2. STACK/SUBSTACK CONFIGURATIONS FOR GIVEN CONTROL BIT SETTINGS CONTROL BIT SETTINGS PARAMETER STACK CONFIGURATION STACK RANGE SVR V7 X X X X X X X X X 0 1 1 V6 X X X X X X 0 1 1 X X X V5 X X X 0 1 1 X X X X X X V4 0 1 1 X X X X X X X X X U2 0 0 0 0 0 0 1 1 1 1 1 1 SUR U1 0 0 0 1 1 1 0 0 0 1 1 1 U0 X 0 1 X 0 1 X 0 1 X 0 1 STACK SIZE WORDS 32 32 32 64 64 64 128 128 128 256 256 256 LOWEST ADDRESS 7 P7 P7 P7 P7 P7 P7 P7 P7 P7 0 0 0 6 P6 P6 P6 P6 P6 P6 0 0 0 0 0 0 5 P5 P5 P5 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 P7 P7 P7 P7 P7 P7 P7 P7 P7 1 1 1 6 P6 P6 P6 P6 P6 P6 1 1 1 1 1 1 HIGHEST ADDRESS 5 P5 P5 P5 1 1 1 1 1 1 1 1 1 4 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
18
HS-RTX2010RH
1 1 1
CONTROL BIT SETTINGS
RETURN STACK CONFIGURATION STACK RANGE
SVR V15 X X X X X X X X X 0 1 1 V14 X X X X X X 0 1 1 X X X V13 X X X 0 1 1 X X X X X X V12 0 1 1 X X X X X X X X X U10 0 0 0 0 0 0 1 1 1 1 1 1
SUR U9 0 0 0 1 1 1 0 0 0 1 1 1 U8 X 0 1 X 0 1 X 0 1 X 0 1
STACK SIZE WORDS 32 32 32 64 64 64 128 128 128 256 256 256
LOWEST ADDRESS 7 P15 P15 P15 P15 P15 P15 P15 P15 P15 0 0 0 6 P14 P14 P14 P14 P14 P14 0 0 0 0 0 0 5 P13 P13 P13 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 P15 P15 P15 P15 P15 P15 P15 P15 P15 1 1 1 6 P14 P14 P14 P14 P14 P14 1 1 1 1 1 1
HIGHEST ADDRESS 5 P13 P13 P13 1 1 1 1 1 1 1 1 1 4 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
TABLE 2. STACK/SUBSTACK CONFIGURATIONS FOR GIVEN CONTROL BIT SETTINGS (Continued) CONTROL BIT SETTINGS SVR V7 X X X X X X X X X 0 1 1 V6 X X X X X X 0 1 1 X X X V5 X X X 0 1 1 X X X X X X V4 0 1 1 X X X X X X X X X U2 0 0 0 0 0 0 1 1 1 1 1 1 SUR U1 0 0 0 1 1 1 0 0 0 1 1 1 U0 X 0 1 X 0 1 X 0 1 X 0 1 7 P7 P7 P7 P7 P7 P7 P7 P7 P7 1 0 1 6 P6 P6 P6 P6 P6 P6 1 0 1 1 1 1 5 P5 P5 P5 1 0 1 1 1 1 1 1 1 FATAL LIMIT 4 1 0 1 1 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 7 P7 P7 P7 P7 P7 P7 P7 P7 P7 0 1 0 6 P6 P6 P6 P6 P6 P6 0 1 0 0 0 0 PARAMETER STACK CONFIGURATION UNDERFLOW LIMIT 5 P5 P5 P5 0 1 0 0 0 0 0 0 0 4 0 1 0 U7 U7 U7 U7 U7 U7 U7 U7 U7 3 U6 U6 U6 U6 U6 U6 U6 U6 U6 U6 U6 U6 2 U5 U5 U5 U5 U5 U5 U5 U5 U5 U5 U5 U5 1 U4 U4 U4 U4 U4 U4 U4 U4 U4 U4 U4 U4 0 U3 U3 U3 U3 U3 U3 U3 U3 U3 U3 U3 U3 7 P7 P7 P7 P7 P7 P7 P7 P7 P7 0 0 1 6 P6 P6 P6 P6 P6 P6 0 0 1 V6 V6 V6 OVERFLOW LIMIT 5 P5 P5 P5 0 0 1 V5 V5 V5 V5 V5 V5 4 0 0 1 V4 V4 V4 V4 V4 V4 V4 V4 V4 3 V3 V3 V3 V3 V3 V3 V3 V3 V3 V3 V3 V3 2 V2 V2 V2 V2 V2 V2 V2 V2 V2 V2 V2 V2 1 V1 V1 V1 V1 V1 V1 V1 V1 V1 V1 V1 V1 0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0
19
HS-RTX2010RH
CONTROL BIT SETTING SVR V15 V14 V13 V12 U10 X X X X X X X X X X X X X X X 0 1 1 0 1 1 X X X 0 0 0 0 0 0 SUR U9 0 0 0 1 1 1 U8 X 0 1 X 0 1 7 6 5 FATAL LIMIT 4 1 0 1 1 1 1 3 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1
PARAMETER STACK CONFIGURATION UNDERFLOW LIMIT 7 6 5 4 0 1 0 3 2 1 0 7 6 OVERFLOW LIMIT 5 4 0 0 1 3 2 1 V9 V9 V9 V9 V9 V9 0 V8 V8 V8 V8 V8 V8
P15 P14 P13 P15 P14 P13 P15 P14 P13 P15 P14 P15 P14 P15 P14 1 0 1
P15 P14 P13 P15 P14 P13 P15 P14 P13 P15 P14 P15 P14 P15 P14 0 1 0
U14 U13 U12 U11 P15 P14 P13 U14 U13 U12 U11 P15 P14 P13 U14 U13 U12 U11 P15 P14 P13 0 0 1
V11 V10 V11 V10 V11 V10
U15 U14 U13 U12 U11 P15 P14 U15 U14 U13 U12 U11 P15 P14 U15 U14 U13 U12 U11 P15 P14
V12 V11 V10 V12 V11 V10 V12 V11 V10
TABLE 2. STACK/SUBSTACK CONFIGURATIONS FOR GIVEN CONTROL BIT SETTINGS (Continued) CONTROL BIT SETTING SVR V15 V14 V13 V12 U10 X X X 0 1 1 NOTES: 18. SPR : Stack Pointer Register, SVR : Stack Overflow Register, SUR : Stack Underflow Register. 19. P0 . . P15: SPR Bits, V0 . . V15: SVR Bits, U0 . . U15: SUR Bits. 20. The Overflow Limit is the stack memory address at which an overflow condition will occur during a stack write operation. 21. The Underflow Limit is the stack memory address below which an underflow condition will occur during a stack read operation. 22. The Fatal Limit is the stack memory address at which a fatal error condition will occur during a stack read or write operation. 23. Stack error conditions remain in effect until a new value is written to the SPR . 24. Stacks and sub-stacks are circular: after writing to the highest location in the stack, the next location to be written to will be the lowest location; after reading the lowest location, the highest location will be read next. 0 1 1 X X X X X X X X X X X X X X X 1 1 1 1 1 1 SUR U9 0 0 0 1 1 1 U8 X 0 1 X 0 1 7 P15 P15 P15 1 0 1 6 1 0 1 1 1 1 5 1 1 1 1 1 1 FATAL LIMIT 4 1 1 1 1 1 1 3 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 7 P15 P15 P15 0 1 0 6 0 1 0 0 0 0 PARAMETER STACK CONFIGURATION UNDERFLOW LIMIT 5 0 0 0 0 0 0 4 3 2 1 0 7 6 0 0 1 OVERFLOW LIMIT 5 4 3 2 1 V9 V9 V9 V9 V9 V9 0 V8 V8 V8 V8 V8 V8
U15 U14 U13 U12 U11 P15 U15 U14 U13 U12 U11 P15 U15 U14 U13 U12 U11 P15 U15 U14 U13 U12 U11 U15 U14 U13 U12 U11 U15 U14 U13 U12 U11 0 0 1
V13 V12 V11 V10 V13 V12 V11 V10 V13 V12 V11 V10
20
V14 V13 V12 V11 V10 V14 V13 V12 V11 V10 V14 V13 V12 V11 V10
HS-RTX2010RH
HS-RTX2010RH
TCLK RISING EDGE TCLK RISING EDGE INTA CYCLE OR ASIC READ COMMAND
TOP REGISTER
PRELOAD REGISTER TP0
LOAD
TC0
TIMER/COUNTER
EXECUTE COUNT
ACTIVATE TIMEOUT INTERRUPT
INTERRUPT RESET
ASIC BUS
PRELOAD REGISTER TP1
LOAD
TC1
TIMER/COUNTER
EXECUTE COUNT
ACTIVATE TIMEOUT INTERRUPT
INTERRUPT CONTROLLER
INTERRUPT RESET
PRELOAD REGISTER TP2
LOAD
TC2
TIMER/COUNTER
EXECUTE COUNT
ACTIVATE TIMEOUT INTERRUPT
INTERRUPT RESET
FIGURE 23. HS-RTX2010RH TIMER/COUNTER OPERATION TABLE 3. TIMER/COUNTER
IBC BIT VALUES
BIT 09 0 0 1 1 BIT 08 0 1 0 1
TIMER CLOCK SOURCE
TC2
TCLK TCLK TCLK EI5
TC1
TCLK TCLK EI4 EI4
TC0
TCLK EI3 EI3 EI3
HS-RTX2010RH Interrupt Controller
The HS-RTX2010RH Interrupt Controller manages interrupts for the HS-RTX2010RH Microcontroller core. Its sources include two on-chip peripherals and six external interrupt inputs. The two classes of on-chip peripherals that produce interrupts are the Stack Controllers and the Timer/Counters.
Interrupt Controller Operation
When one of the interrupt sources requests an interrupt, the Interrupt Controller checks whether the interrupt is masked in the Interrupt Mask Register. If it is not, the controller attempts to interrupt the processor. If processor interrupts are enabled (bit 4 of the Configuration Register), the processor will execute an Interrupt Acknowledge cycle, during which it disables interrupts to ensure proper completion of the INTA cycle. In response to the Interrupt Acknowledge cycle, the Interrupt Controller places an Interrupt Vector on the internal ASIC Bus, based on the highest priority pending interrupt. The
processor performs a special Subroutine Call to the address in Memory Page 0 contained in the vector. This special subroutine call is different in that it saves a status bit on the Return Stack indicating the call was caused by an interrupt. Thus, when the Interrupt Handler executes a Subroutine Return, the processor knows to automatically re-enable interrupts. Before the Interrupt Handler returns, it must ensure that the condition that caused the interrupt is cleared. Otherwise the processor will again be interrupted immediately upon its return. Processor interrupts are enabled and disabled by clearing and setting the Interrupt Disable Flag. When the RTX is reset, this flag is set (bit 04 of the CR = 1), disabling the interrupts. This bit is a write-only bit that always reads as 0, allowing interrupts to be enabled in only 2 cycles with a simple read/write operation in which the processor reads the bit value, then writes it back to the same location. The actual status of the Interrupt Disable Flag can be read from bit 14 of CR .
21
HS-RTX2010RH
TABLE 4. INTERRUPT SOURCES, PRIORITIES AND VECTORS VECTOR ADDRESS BITS PRIORITY 0 (High) 1 2 3 4 5 6 7 8 9 10 11 12 13 (Low) N/A NMI EI1 PSU RSU PSV RSV EI2 TCI0 TCI1 TCI2 EI3 EI4 EI5 SWI None INTERRUPT SOURCE Non-Maskable Interrupt External Interrupt 1 Parameter Stack Underflow Return Stack Underflow Parameter Stack Overflow Return Stack Overflow External Interrupt 2 Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 Software Interrupt No Interrupt SENSITIVITY Pos Edge High Level High Level High Level High Level High Level High Level Edge Edge Edge High Level High Level High Level High Level N/A
IMR BIT
N/A 01 02 03 04 05 06 07 08 09 10 11 12 13 N/A
09 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
08 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
07 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0
06 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
05 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0
During read and write operations to the Configuration Register, ( CR ), interrupts are inhibited to allow the program to save and restore the state of the Interrupt Enable bit. In addition to disabling interrupts at the processor level, all interrupts except the Non-Maskable Interrupt (NMI) can be individually masked by the Interrupt Controller by setting the appropriate bit in the Interrupt Mask Register ( IMR ). Resetting the HS-RTX2010RH causes all bits in the IMR to be cleared, thereby unmasking all interrupts. The NMI on the HS-RTX2010RH has two modes of operation which are controlled by the NMI_MODE Flag (bit 11 of the CR ). When this bit is cleared (0), the NMI can not be masked, and can interrupt any cycle. This allows a fast response to the NMI, but may not allow a return from interrupt to operate correctly. NMI_MODE is cleared when the processor is Reset. When NMI_MODE is set (1), a return from the NMI service routine will result in the processor continuing execution in the state it was in when it was interrupted. When in this second mode NMI may be inhibited by the processor during certain critical operations (see Interrupt Suppression), and may, therefore, not be serviced as quickly as in the first mode of operation. When servicing an NMI_MODE set to 1, further NMIs and maskable interrupts are disabled until the NMI Interrupt Service Routine has completed, and a return from interrupt has been executed. The Interrupt Controller prioritizes interrupt requests and generates an Interrupt Vector for the highest priority interrupt request. The address that the vector points to is determined by the source of the interrupt and the contents of the Interrupt Base/Control Register ( IBC ). See Figure 12 for the Interrupt Vector Register bit assignments. Because address bits MA19-MA16 are always zero in an Interrupt
Acknowledge cycle, the entry point to the Interrupt Handlers must reside on Memory Page zero. Because address bits MA04-MA01 are always zero in an Interrupt Acknowledge cycle, Interrupt Vectors are 32 bytes apart. This means that Interrupt Handler routines that are 32 bytes or less can be compiled directly into the Interrupt Table. Interrupt Handlers greater than 32 bytes must be compiled separately and called from the Interrupt Table. The rest of the vector is generated as indicated in Table 1. To guarantee that the Interrupt Vector will be stable during an INTA cycle, the Interrupt Controller inhibits the generation of a new Interrupt Vector while INTA is high, and will not begin generating a new Interrupt Vector on either edge of INTA. The Interrupt Vector can also be read from the Interrupt Vector Register ( IVR ) directly. This allows interrupt requests to be monitored by software, even if they are disabled by the processor. If no interrupts are being requested, bit 09 of the IVR will be 1. External interrupts EI5-EI1 are active HIGH level-sensitive inputs. (Note: When used as Timer/Counter inputs, EI5-EI3 are edge sensitive). Therefore, the Interrupt Handlers for these interrupts must clear the source of interrupt prior to returning to the interrupted code. The external NMI, however, is an edge-sensitive input which requires a rising edge to request an interrupt. The NMI input also has a glitch filter circuit which requires that the signal that initiates the NMI must last at least two rising and two falling edges of ICLK. Finally, a mechanism is provided by which an interrupt can be requested by using a software command. The Software Interrupt (SWI) is requested by executing an instruction that will set an internal flip-flop attached to one input of the
22
HS-RTX2010RH
Interrupt Controller. The SWI is reset by executing an instruction that clears the flip-flop. The flip-flop is accessed by I/O Reads and Writes. Because the SWI interrupt may not be serviced immediately, the instructions which immediately follow the SWI instruction should not depend on whether or not the interrupt has been serviced, and should cause a one or two-cycle idle condition (Typically, this is done with one or two NOP instructions). If an interrupt condition occurs, but "goes away" before the processor has a chance to service it, a "No Interrupt" vector is generated. A "No Interrupt" vector is also generated if an Interrupt Acknowledge cycle takes less than two cycles to execute and no other interrupt conditions need to be serviced. To prevent unforeseen errors, it is recommended that valid code be supplied at every Interrupt Vector location, including the "No Interrupt" vector, which should always be initialized with valid code. It is recommended that Interrupt Handlers save and restore the contents of CR . Stack Architecture" for more information regarding how the limits set into IBC and SUR are used. Stack Overflow: A stack overflow occurs when data is pushed onto the stack location pointed to by the SVR , as determined in Table 5. After the processor is reset, this is location 255 in either the Parameter Stack or Return Stack. A stack overflow interrupt request stays in effect until cleared by writing a new value to the SPR . In addition to generating an interrupt, the state of the stack overflow flags may be read out of the IBC , bit 3 for the Parameter Stack, and bit 4 for the Return stack. See Figures 13, 15 and 16. Stack Underflow: The stack underflow limit occurs when data is popped off the stack location immediately below that pointed to by the SUR , as determined in Table 2. The state of the stack underflow error flags may be read out of bits 1 and 2 of the IBC for the Parameter and Return stacks respectively. In the reset state of the SUR , an underflow will be generated at the same time that a fatal error is detected. An underflow buffer region can be set up by selecting an underflow limit greater than zero by writing the corresponding value into the SUR . The stack underflow interrupt request stays in effect until a new value is written into the SPR , at which time it is cleared.
Interrupt Suppression
The HS-RTX2010RH allows maskable interrupts and Mode 1 NMIs (the NMI_MODE Flag in bit 11 of the CR is set) to be suppressed, delaying them temporarily while critical operations are in progress. Critical operations are instruction sequences and hardware operations that, if interrupted, would result in the loss of data or misoperation of the hardware. (Note: Only the processor may suppress NMIs.) Standard critical operations during which interrupts are automatically suppressed by the processor include Streamed instructions (see the description of the I register), Long Call sequences (see "Subroutine Calls and Returns"), and loading CR . In addition to this, external devices can also suppress maskable interrupts during critical operations by applying a HIGH level on the INTSUP pin for as long as required. Since the Mode 0 NMI (the NMI_MODE Flag in bit 11 of the CR is cleared) can cause the processor to perform an Interrupt Acknowledge Cycle in the middle of these critical operations, thereby preventing a normal return to the interrupted instruction, a Subroutine Return should be used with care from a Mode 0 NMI service routine. The Mode 0 NMI should be used only to indicate critical system errors, and the Mode 0 NMI handler should re-initialize the system. Interrupts which have occurred while interrupt suppression is in effect will be recognized on a priority basis as soon as the suppression terminates, provided the condition which generated the interrupt still exists.
Timer/Counter Interrupts
The timers generate edge-sensitive interrupts whenever they are decremented to 0. Because they are edge-sensitive and are cleared during an Interrupt Acknowledge cycle or during the direct reading of IVR by software, no action is required by the handlers to clear the interrupt request.
The HS-RTX2010RH ALU
The HS-RTX2010RH has a 16-bit ALU capable of performing standard arithmetic and logic operations: * ADD and SUBTRACT (A-B and B-A; with and without carry) * AND, OR, XOR, NOR, NAND, XNOR, NOT The TOP and NEXT registers can also undergo single bit shifts in the same cycle as a logic or arithmetic operation. In Figure 24, the control and data paths to the ALU are shown. Except for TOP and NEXT , each of the internal core registers can be addressed explicitly, as can other internal registers in special operations such as in Step instructions. In each of these cases, the input would be addressed as a device on the ASIC Bus. When executing these instructions, the arithmetic/logic operand (a) starts out in TOP and is placed on the T-bus. Operand (b) arrives at the ALU on the Y-bus, but can come from one of the following four sources: NEXT ; an internal register; an ASIC Bus device; or from the 5 least significant bits of IR . The source of operand (b) is determined by the instruction code in IR . The result of the ALU operation is placed into TOP .
Stack Error Interrupts
The Stack Controllers request an interrupt whenever a stack overflow or underflow condition exists. These interrupts can be cleared by rewriting SPR . See the section on "Dual
23
HS-RTX2010RH
PROGRAM MEMORY 5 LEAST SIGNIFICANT BITS
TOP T-BUS
IR
ASIC BUS DEVICE INTERNAL REGISTERS NEXT IR DECODE Y-BUS SELECT OPERAND (B)
OPERAND (A) T
Y ALU CONTROL
ALU
SHIFTER
NOTE: Data Paths are represented by solid lines; Control Paths are represented by dashed lines. FIGURE 24. ALU OPERATIONS-CONTROL PATHS AND DATA FLOW
Step Arithmetic instructions which are performed through the ALU are divide and square root. Execution of each step of the arithmetic operation takes one cycle, a 32/16-bit Step Divide takes 21 cycles, and a 32/16-bit Step Square Root takes 25 cycles. Sign and scaling functions are controlled by the ALU function and shift options, which are part of the coded instruction contained in IR . See Table 20 and Table 21 and the Programmer's Reference Manual for details. Unsigned Step Divide operation assumes a double precision (32-bit) dividend, with the most significant word placed in TOP , the less significant word in NEXT , and the divisor in MD . In each step, if the contents in TOP are equal to or greater than the contents in MD (and therefore no borrow is generated), then the contents of MD are subtracted from the contents of TOP . The result of the subtraction is placed into TOP . The contents of TOP and NEXT are then jointly shifted left one bit (32-bit left shift), where the value shifted into the least significant bit of NEXT is the value of the Borrow bit on the first pass, or the value of the Complex Carry bit on each of the subsequent passes. On the 15th and final pass, only NEXT is shifted left, receiving the value of the Complex Carry bit into the LSB. TOP is not shifted. The final result leaves the quotient in EXT , and the remainder in TOP . During a Step Square Root operation, the 32-bit argument is assumed to be in TOP and NEXT , as in the Step Divide operation. The first step begins with MD containing zeros. The Step Square Root is performed much like the Step Divide, except that the input from the Y-bus is the logical OR of the contents of SR and the value in MD shifted one
place to the left (2* MD ). When the subtraction is performed, SR is OR'ed into MD , and SR is shifted one place to the right. At the end of the operation, the square root of the original value is in MD and NEXT , and the remainder is in TOP .
HS-RTX2010RH Floating Point/DSP On Chip Peripherals
The HS-RTX2010RH Multiplier-Accumulator
The Hardware Multiplier-Accumulator (MAC) on the HS-RTX2010RH functions as both a Multiplier, and a Multiplier- Accumulator. When used as a Multiplier alone, it multiplies two 16-bit numbers, yielding a 32-bit product in one clock cycle. When used as a Multiplier-Accumulator, it multiplies two 16-bit numbers, yielding an intermediate 32-bit product, which is then added to the 48-bit Accumulator. This entire process takes place in a single clock cycle. The Multiplier-Accumulator functions are activated by I\O Read and Write instructions to ASIC Bus addresses assigned to the MAC. The MAC's input operands come from three possible sources (see Figure 25): 1. The TOP and EXT registers. 2. The Parameter (Data) Stack and memory via NEXT (Streamed mode only - see the Programmer's Reference Manual). 3. Memory via EXT and an input from the ASIC Bus (Streamed mode only - see the Programmer's Reference Manual).
24
HS-RTX2010RH
DATA STACK ASIC BUS
REGISTER
TOP
NEXT
32-BIT LZD MAC 16 x 16 SIGN EXT. 48 5 32-BIT BRL SHIFTER 32 MHR MXR TOP TOP TOP
16
16
MXR
MHR
MLR
FIGURE 25. HS-RTX2010RH FLOATING POINT/DSP LOGIC
These inputs can be treated as either signed (two's complement) or unsigned integers, depending on the form of the instruction used. In addition, if the ROUND option is selected, the Multiplier can round the result to 16 bits. Note that the MAC instructions do not pop the Parameter Stack; the contents of TOP and NEXT remain intact. For the Multiplier, the product is read from the Multiplier High Product Register, MHR , which contains the upper 16 bits of the product, and the Multiplier Low Product Register, MLR , which contains the lower 16 bits. For the MultiplierAccumulator, the accumulated product is read from the Multiplier Extension Register, MXR , which contains the upper 16 bits, the MHR , which contains the middle 16 bits, and the MLR , which contains the low 16 bits. The registers may be read in any order, and there is no requirement that all registers be read. Reading from any of the three registers moves its value into TOP , and pushes the original value in TOP into NEXT . If the read is from MHR or MLR , the original value of NEXT is lost, i.e. it is not pushed onto stack memory. This permits overwriting the original operands left in TOP and NEXT , which are not popped by the MAC operations. If the read is from MXR , the original value of NEXT is pushed onto the stack. In addition to this, any of the three MAC registers can be directly loaded from TOP . This pops NEXT into TOP and the Parameter Stack into NEXT . If 32-bit precision is not required, the multiplier output may be rounded to 16 bits. This is accomplished by setting the ROUND bit in the Interrupt Base/Control Register, IBC , to 1. If the ROUND bit is set to 1, all operations that use the Multiplier automatically round the least significant 16 bits of the result into the most significant 16 bits. The rounding is achieved by adding 8000H to the least significant 16 bits (during the same cycle as the multiply). Thus, if the ROUND bit is set:
1. If the most significant bit of the MLR is set (1), the MHR is incremented. 2. If the most significant bit of the MLR is not set (0), the MHR is left unchanged. The ROUND bit functions independently of whether the signed or unsigned bit is used. The multiply instructions suppress interrupts during the multiplication cycle. Reading MHR , or MLR also suppresses interrupts during the read. This allows a multiplication operation to be performed, and both the upper and lower registers to be read sequentially, with no danger of a non-NMI interrupt service routine corrupting the contents of the registers between reads. The multiply-accumulate instructions do not suppress interrupts during instruction execution. For additional information on the HS-RTX2010RH MAC see the Programmer's Reference Manual.
The HS-RTX2010RH On-Chip Barrel Shifter And Leading Zero Detector
The HS-RTX2010RH has both a 32-bit Barrel Shifter and a 32-bit Leading Zero Detector for added floating-point and DSP performance. The inputs to the Barrel Shifter and Leading Zero Detector are the top two elements of the Parameter Stack, the TOP and NEXT registers. The Barrel Shifter uses a 5-bit count stored in the MXR Register to determine the number of places to right or left shift the double word operand contained in the TOP and NEXT registers. The output of the Barrel Shifter is stored in the MHR and MLR registers, with the top 16 bits in MHR and the bottom 16 bits in MLR .
25
HS-RTX2010RH
The Leading Zero Detector is used to normalize the double word operand contained in the TOP and EXT registers. The number of leading zeroes in the double word operand are counted, and the count stored in the MXR register. The double word operand is then logically shifted left by this count, and the result stored in the MHR and MLR registers. Again the upper 16 bits are in MHR , and the lower 16 bits are in MLR . This entire operation is done in one clock cycle with the normalize instruction. Setting the Cycle Extend bit (CYCEXT), which is bit 7 of the IBC Register, will cause extended cycles to be used for all accesses to USER memory. Setting the ASIC Read Cycle Extend bit (ARCE), which is bit 13 of the CR Register, will cause extended cycles to be used for all Read accesses on the external ASIC Bus. Both the CYCEXT bit and the ARCE bit are cleared on Reset.
HS-RTX2010RH Memory Access
The HS-RTX2010RH Memory Bus Interface
The HS-RTX2010RH can address 1 Megabyte of memory, divided into 16 non-overlapping pages of 64K bytes. The memory page accessed depends on whether the memory access is for Code (instructions and literals), Data, User Memory, or Interrupt Code. The page selected also depends on the contents of the Page Control Registers: the Code Page Register ( CPR ), the Data Page Register ( DPR ), the User Page Register ( UPR ), and the Index Page Register ( IPR ). Furthermore, the User Base Address Register ( UBR ) and the Interrupt Base/Control Register ( IBC ) are used to determine the complete address for User Memory accesses and Interrupt Acknowledge cycles. External memory data is accessed through EXT . When executing code other than an Interrupt Service routine, the memory page is determined by the contents of the CPR . Bits 03-00 generate address bits MA19-MA16, as shown in Figure 18. The remainder of the address (MA15MA01) comes from the Program Counter Register ( PC ). After resetting the processor, both the PC and the CPR are cleared and execution begins at page 0, word 0. A new Code page is selected by writing a 4-bit value to the CPR . The value for the Code page is input to the CPR through a preload procedure which withholds the value for one clock cycle before loading the CPR to ensure that the next instruction is executed from the same Code page as the instruction which set the new Code page. Execution immediately thereafter will continue with the next instruction in the new page. An Interrupt Acknowledge cycle is a special case of an Instruction Fetch cycle. When an Interrupt Acknowledge cycle occurs, the contents of the CPR and PC are saved on the Return Stack and then the CPR is cleared to point to page 0. The Interrupt Controller generates a 16-bit address, or "vector", which points to the code to be executed to process the interrupt. To determine how the Interrupt Vector is formed, refer to Figure 12 for the register bit assignments, and also to the Interrupt Controller section. The page for data access is provided by either CPR or DPR , as shown in Figures 18 and 20. Data Memory Access instructions can be used to access data in a memory page other than that containing the program code. This is done by writing the desired page number into the Data Page Register ( DPR ) and setting bit 5 (DPRSEL) of the IBC
HS-RTX2010RH ASIC Bus Interface
The HS-RTX2010RH ASIC Bus services both internal processor core registers and the on-chip peripheral registers, and eight external off-chip ASIC Bus locations. All ASIC Bus operations require a single cycle to execute and transfer a full 16-bit word of data. The external ASIC Bus maps into the last eight locations of the 32 location ASIC Address Space. The three least significant bits of the address are available as the ASIC Address Bus. The addresses therefore map as shown in Table 5.
TABLE 5. ASIC BUS MAP ASIC BUS SIGNAL GA02 0 0 0 0 1 1 1 1 GA01 0 0 1 1 0 0 1 1 GA00 0 1 0 1 0 1 0 1 ASIC ADDRESS 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH
HS-RTX2010RH Extended Cycle Operation
The HS-RTX2010RH bus cycle operation can be optionally extended for two types of accesses: 1. USER Memory Cycles 2. ASIC Bus Read Operations The extension of normal HS-RTX2010RH bus cycle timing allows the interface of the processor to some peripherals, and slow memory devices, without using externally generated wait states. The bus cycle is extended by the same amount (1 TCLK) as it would be if one wait state was added to the cycle, but the control signal timing is somewhat different (see Timing Diagrams). In a one wait state bus cycle, PCLK is High for 1/2 TCLK period, and Low for 1-1/2 TCLK periods (i.e., PCLK is held Low for one additional TCLK period). In an extended cycle, PCLK is High for 1 TCLK period, and Low for 1 TCLK period (i.e., both the High and Low portions of the PCLK period are extended by 1/2 TCLK period).
26
HS-RTX2010RH
Register to 1. If DPR is set to equal CPR , or if DPRSEL = 0, data will be accessed in the Code page. The status of the DPRSEL bit is saved and restored as a result of a Subroutine Call or Return. When the HS-RTX2010RH is reset, DPR points to page 0 and DPRSEL resets to 0, selecting the CPR . USER MEMORY consists of blocks of 32 words that can be located anywhere in memory. The word being accessed in a block is pointed to by the five least significant bits of the User Memory instruction (see Table 17), eliminating the need to explicitly load an address into TOP before reading or writing to the location. Upon HS-RTX2010RH reset, UBR is cleared and points to the block starting at word 0, while UPR is cleared so that it points to page 0. The word in the block is pointed to by the five least significant bits of the User Memory instruction and bits 05-01 of the UBR . These bits from these two registers are logically OR'ed to produce the address of the word in memory. See Figure 21.
Word And Byte Main Memory Access
Using Main Memory Access instructions, the HS-RTX2010RH can perform either word or single byte Main Memory accesses, as well as byte swapping within 16-bit words. Bit 12 of the Memory Access Opcode (see Table 16), is used to determine whether byte or word operations are to be performed (where bit 12 = 0 signifies a word operation, and bit 12 = 1 signifies a byte operation). In addition, the determination of whether a byte swap is to occur depends on whether Addressing Mode 0 or Mode 1 is in effect (as determined by bit 2 of the CR ), and on whether an even or odd address is being accessed (see Figures 26 and 27).
DATA ACCESS (16-BIT)
IR CR ADDRESS BIT 12 BIT 2 EVEN/ODD
0
DATA ACCESS (8 -BIT)
CR ADDRESS IR BIT 12 BIT 2 EVEN/ODD
PROCESSOR 0
WORD WRITE
15 8 7
PROCESSOR
BYTE WRITE 0 0 0
15 UNCHANGED 8 7
0 1
1
15
8
7
0 MEMORY
1
1
15
8
7
0 MEMORY
1
0
WORD READ
15 8 7
PROCESSOR 0
BYTE READ 0 0
0
PROCESSOR 8 7 0
0
15
0 1
1
15
8
7
0 MEMORY
1
1
15
8
7
0 MEMORY
1
0
WORD WRITE
15 8 7
PROCESSOR 0
BYTE WRITE
15 8 7
PROCESSOR 0
0 0
1 1
UNCHANGED
1
1
1
15 8 7 0 MEMORY
0
15 8 7 0 MEMORY
0
0
WORD READ
15 8 7
PROCESSOR 0
BYTE READ
15 8 7
PROCESSOR 0
0 0 1
15 8 7 0 MEMORY
1
0
1 1 0
1
0
15 8 7 0 MEMORY
0
FIGURE 26. MEMORY ACCESS (WORD)
FIGURE 27. MEMORY ACCESS (BYTE)
27
HS-RTX2010RH
Whenever a word of data is read by a Data Memory operation into the processor, it is first placed in the NEXT Register. By the time the instruction that reads that word of data is completed, however, the data may have been moved, optionally inverted, or operated on by the ALU, and placed in the TOP Register. Whenever a Data Memory operation writes to memory, the data comes from the NEXT Register. The Byte Order Bit is bit 2 of the Configuration Register, CR (see Figure 11 in the "RTX Internal Registers Section). This bit is used to determine whether the default (Mode 0) or byte swap (Mode 1) method will be used in the Data Memory accesses. Word Access is designated when the IR bit 12 = 0 in the Memory Access Opcode, and can take one of two forms, depending upon the status of CR , bit 2. When CR bit 2 = 0, the Mode 0 method of word access is designated. Word access to an even address (A0 = 0) results in an unaltered transfer of data, as shown in Figure 26. Word access to/from an odd address (A0 = 1) while in this mode will effectively cause the Byte Order Bit to be complemented and will result in the bytes being swapped. When the CR bit 2 = 1, the Mode 1 method of word access is designated. Access to an even address (A0 = 0) results in a data transfer in which the bytes are swapped. Word access to an odd address (A0 = 1) while in this mode will effectively cause the Byte Order Bit to be complemented with the net result that no byte swap takes place when the data word is transferred. See Figure 26. Byte Access is designated when the IR bit 12 = 1 in the Memory Access Opcode, and can also take one of two forms, depending on the value of CR Bit 2. When the CR bit 2 = 0, a Byte Read from an even address in Mode 0 causes the upper byte (MD15-MD08) of memory data to be read into the lower byte position (MD07-MD00) of NEXT , while the upper byte (MD15-MD08) is set to 0. A Byte Write operation accessing an even address will cause the byte to be written from the lower byte position (MD07-MD00) of NEXT into the upper byte position (MD15-MD08) of memory. The data in the lower byte position (MD07-MD00) in memory will be left unaltered. Accessing an odd address for either of these operations will cause the Byte Order Bit to be complemented, with the net result that no swap will occur. See Figure 27. When CR bit 2 = 1, the Mode 1 method of memory access is used. Accessing an even address in this mode means that a Byte Read operation will cause the lower byte of data to be transferred without a swap operation. A Byte Write in this mode will also result in an unaltered byte transfer. Conversely, accessing an odd address for a byte operation while in Mode 1 will cause the Byte Order Bit to be complemented. In a Byte Read operation, this will result in the upper byte (MD15-MD08) of data being swapped into the lower byte position (MD07-MD00), while the upper byte is set to 0 (MD15-MD08 set to 0). See Figure 27. A Byte Write operation accessing an odd address will cause the byte to be swapped from the lower byte position (MD07-MD00) of the processor register into the upper byte position (MD15-MD08) of the Memory location. The data in the lower byte position (MD07-MD00) in that Memory location will be left unaffected.
NOTE: These features are for Main Memory data access only, and have no effect on instruction fetches, long literals, or User Data Memory.
Subroutine Calls And Returns
The RTX can perform both "short" subroutine calls and "long" subroutine calls. A short subroutine call is one for which the subroutine code is located within the same Code page as the Call instruction, and no processor cycle time is expended in reloading the CPR . Performing a long subroutine call involves transferring execution to a different Code page. This requires that the CPR be loaded with the new Code page as described in the Memory Access Section, followed immediately by the Subroutine Call instruction. This adds two additional cycles to the execution time for the Subroutine Call. For all instructions except Subroutine Calls or Branch instructions, bit 5 of the instruction code represents the Subroutine Return Bit. If this bit is set to 1, a Return is performed whereby the return address is popped from the Return Stack, as indicated in Figure 19. The page for the return address comes from the IPR . The contents of the I Register are written to the PC , and the contents of the IPR are written to the CPR so that execution resumes at the point following the Subroutine Call. The Return Stack is also popped at this time.
HS-RTX2010RH Software
The HS-RTX2010RH is designed around the same architecture as the RTX 2000, and is a hardware implementation of the Virtual Forth Engine. As such, it does not require the additional assembly or machine language software development typical of most real-time microcontrollers. The instruction set for the HS-RTX2010RH TForth compiler combines multiple high level instructions into single machine instructions without having to rely on either pipelines or caches. This optimization yields an effective throughput which is faster than the processor's clock speed, while avoiding the unpredictable execution behavior exhibited by most RISC processors caused by pipeline flushes and cache misses.
2010 Compilers
Intersil offers a complete ANSI C cross development environment for the HS-RTX2010RH. The environment provides a powerful, user-friendly set of software tools
28
HS-RTX2010RH
designed to help the developers of embedded real-time control systems get their designs to market quickly. The environment includes the optimized ANSI C language compiler, symbolic menu driven C language debugger, RTX assembler, linker, profiler, and PROM programmer interface. The HS-RTX2010RH TForth compiler from Intersil translates Forth-83 source code to HS-RTX2010RH machine instructions. This compiler also provides support for all of the HS-RTX2010RH instructions specific to the processor's registers, peripherals, and ASIC Bus. See the tables in the following sections for instruction set information.
TABLE 6. INSTRUCTION SET SUMMARY NOTATIONS m-read m-write g-read DEFINITION Read data (byte or word) from memory location addressed by contents of TOP Register into TOP Register. Write contents (byte or word) of NEXT Register into memory location addressed by contents of TOP Register. Read data from the ASIC address (address field ggggg of instruction) into TOP Register. A read of one of the onchip peripheral registers can be done with a g-read command. Write contents of TOP Register to ASIC address (address field ggggg of instruction). A write to one of the on-chip peripheral registers can be done with a g-write command. Read contents (word only) of User Space location (address field uuuuu of instruction) into TOP Register. Write contents (word only) of TOP Register into User Space location (address field uuuuu of instruction). Exchange contents of TOP and NEXT registers. Copy contents of TOP Register to NEXT Register, pushing previous contents of NEXT onto Stack Memory. Copy contents of NEXT Register to TOP Register, pushing original contents of TOP to NEXT Register and original contents of NEXT Register to Stack Memory. Pop Parameter Stack, discarding original contents of TOP Register, leaving the original contents of NEXT in TOP and the original contents of the top Stack Memory location in NEXT . Perform 1's complement on contents of TOP Register, if i bit in instruction is 1. Perform appropriate cccc or aaa ALU operation from Table 20 on contents of TOP and NEXT registers. Perform appropriate shift operation (ssss field of instruction) from Table 21 on contents of TOP and/or NEXT registers. Push short literal d from ddddd field of instruction onto Parameter Stack (where ddddd contains the actual value of the short literal). The original contents of TOP are pushed into NEXT , and the original contents of. NEXT are pushed onto Stack Memory. Push long literal D from next sequential location in program memory onto Parameter Stack. The original contents of TOP are pushed into NEXT , and the original contents of NEXT are pushed onto Stack Memory. Perform a Return From Subroutine if bit = 1.
g-write
u-read u-write SWAP DUP OVER
DROP
inv alu-op shift
d
D
R NOTE:
All unused opcodes are reserved for future architectural enhancements.
TABLE 7. INSTRUCTION REGISTER BIT FIELDS (BY FUNCTION) FUNCTION CODE ggggg uuuuu cccc aaa ddddd ssss DEFINITION Address field for ASIC Bus locations Address field for User Space memyyory locations ALU functions (see Table 20) Short literals (containing a value from 0 to 31) Shift Functions (see Table 21)
29
HS-RTX2010RH
TABLE 8. HS-RTX2010RH I AND PC ACCESS OPERATIONS (Note) OPERATION (g-read, g-write) Read mode Read mode Write mode Write mode Read mode Read mode Write mode Write mode Read mode Read mode Write mode RETURN BIT VALUE 0 1 0 1 0 1 0 1 0 1 0 ASIC ADDRESS ggggg 00000 00000 00000 00000 00001 00001 00001 00001 00010 00010 00010
REGISTER
FUNCTION Pushes the contents of I into TOP (with no pop of the Return Stack) Pushes the contents of I into TOP , then performs a Subroutine Return Pops the contents of TOP into I (with no push of the Return Stack) Performs a Subroutine Return, then pushes the contents of TOP into I Pushes the contents of I into TOP , popping the Return Stack Pushes the contents of I into TOP without popping the Return Stack, then executes the Subroutine Return Pushes the contents of TOP into I popping the Parameter Stack Performs a Subroutine Return, then pushes the contents of TOP into I Pushes the contents of I shifted left by one bit, into TOP (the Return Stack is not popped) Pushes the contents of I shifted left by one bit, into TOP (the Return Stack is not popped), then performs a Subroutine Return Pushes the contents of TOP into I as a "stream" count, indicating that the next instruction is to be performed a specified number of times; the Parameter Stack is popped Performs a Subroutine Return, then pushes the stream count into I Pushes the contents of PC into TOP Pushes the contents of PC into TOP , then performs a Subroutine Return Performs a Subroutine Call to the address contained in TOP , popping the Parameter Stack Pushes the contents of TOP onto the Return Stack before executing the Subroutine Return
I I I I I I I I I I I
Write mode Read mode Read mode Write mode Write mode
1 0 1 0 1
00010 00111 00111 00111 00111
I PC PC PC PC
NOTE: See the RTX Programmer's Reference Manual for a complete listing of typical software functions. TABLE 9. HS-RTX2010RH RESERVED I/O OPCODES INSTRUCTION CODE 15 14 13 12 1011 1011 1011 1011 11 10 9 8 0000 0000 0000 0000 7654 10R0 00R0 10R1 00R1 3210 1101 1101 0000 0000 Select DPR Select CPR Set SOFTINT Clear SOFTINT OPERATION
TABLE 10. SUBROUTINE CALL INSTRUCTIONS INSTRUCTION CODE 15 14 13 12 0aaa Subroutine Call Bit (Bit 15 = 0: Call, Bit 15 = 1: No Call) 11 10 9 8 aaaa 7654 aaaa 3210 aaaa Call word address aaaa aaaa aaaa aaa0, in the page indicated by CPR . This address is produced when the processor performs a left shift on the address in the instruction code. OPERATION
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HS-RTX2010RH
TABLE 11. SUBROUTINE RETURN INSTRUCTION CODE 15 14 13 12 --11 10 9 8 ---7654 - - R3210 ---Return from subroutine OPERATION
Subroutine Return Bit (Note) (Bit 5, R = 0: No return R = 1: Return) NOTE: Does not apply to Subroutine Call or Branch Instructions. A Subroutine Return can be combined with any other instruction (as implied here by hyphens).
TABLE 12. BRANCH INSTRUCTIONS INSTRUCTION CODE 15 14 13 12 1000 1000 1001 1001 Branch Address (Note) NOTE: See the Programmer's Reference Manual for further information regarding the branch address field. 11 10 9 8 0bba 1bba 0bba 1bba 7654 aaaa aaaa aaaa aaaa 3210 aaaa aaaa aaaa aaaa DROP and branch if TOP = 0 Branch if TOP = 0 Unconditional branch Branch and decrement I if I 0; Pop I if I = 0 OPERATION
TABLE 13. REGISTER AND I/O ACCESS INSTRUCTIONS INSTRUCTION CODE 15 14 13 12 1011 1011 1011 1011 1011 1011 11 10 9 8 000i 111i cccc 000i 111i cccc 7654 00Rg 00Rg 00Rg 10Rg 10Rg 10Rg 3210 gggg gggg gggg gggg gggg gggg g-read DROP g-read g-read OVER DUP g-write g-write g-read SWAP inv inv alu-op inv inv alu-op OPERATION
TABLE 14. SHORT LITERAL INSTRUCTIONS INSTRUCTION CODE 15 14 13 12 1011 1011 1011 1011 1011 11 10 9 8 000i 111i cccc 111i cccc 7654 01Rd 01Rd 01Rd 11Rd 11Rd 3210 dddd dddd dddd dddd dddd d DROP d d OVER d SWAP DROP d SWAP inv inv alu-op inv alu-op OPERATION
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HS-RTX2010RH
TABLE 15. LONG LITERAL INSTRUCTIONS INSTRUCTION CODE OPERATION
(1ST CYCLE) 15 14 13 12 1101 1101 1101 1101 1101 11 10 9 8 000i 111i cccc 111i cccc 7654 00R0 00R0 00R0 10R0 10R0 3210 0000 0000 0000 0000 0000 D SWAP D SWAP D SWAP D SWAP D SWAP
(2ND CYCLE)
inv SWAP inv SWAP OVER alu-op DROP inv alu-op
TABLE 16. MEMORY ACCESS INSTRUCTIONS INSTRUCTION CODE OPERATION
(1ST CYCLE) 15 14 13 12 111s 111s 111s 111s 111s 111s 111s 111s 111s 111s 111s 111s 11 10 9 8 000i 111i cccc 000p 111p aaap 000i 111i cccc 000p 111p aaap 7 6 54 0 0 R0 00 R0 00 R0 01 R0 01 Rd 01 Rd 10 R0 10 R0 10 R0 11 R0 11 Rd 11 Rd 3210 0000 0000 0000 0000 dddd dddd 0000 0000 0000 0000 dddd dddd m-read SWAP m-read SWAP m-read SWAP (SWAP DROP) DUP m-read SWAP (SWAP DROP) m-read d (SWAP DROP) DUP m-read SWAP d SWAP alu-op OVER SWAP m-write OVER SWAP m-write m-read SWAP (OVER SWAP) SWAP OVER m-write (OVER SWAP) m-write d (OVER SWAP) SWAP OVER m-write d SWAP alu-op
(2ND CYCLE)
inv SWAP inv SWAP OVER alu-op NOP NOP NOP inv DROP inv alu-op NOP NOP NOP
If (p = 0), perform either (SWAP DROP) or (OVER SWAP) If s = 0, Memory is accessed by word If s = 1, Memory is accessed by byte NOTE: SWAP d SWAP d ROT
32
HS-RTX2010RH
TABLE 17. USER SPACE INSTRUCTIONS INSTRUCTION CODE OPERATION
15 14 13 12 1100 1100 1100 1100 1100 1100
11 10 9 8 000i 111i cccc 000i 111i cccc
7654 00Ru 00Ru 00Ru 10Ru 10Ru 10Ru
3210 uuuu uuuu uuuu uuuu uuuu uuuu
(1ST CYCLE) u-read SWAP u-read SWAP u-read SWAP DUP u-write DUP u-write u-read SWAP
(2ND CYCLE) inv SWAP inv SWAP OVER alu-op inv DROP inv alu-op
TABLE 18. ALU FUNCTION INSTRUCTIONS INSTRUCTION CODE 15 14 13 12 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 11 10 9 8 000i 111i cccc 0 00i 111i cccc 000i 111i cccc 000i 111i cccc 7654 00R0 00R0 00R0 01R0 01R0 01R0 10R0 10R0 10R0 11R0 11R0 11R0 3210 ssss ssss ssss ssss ssss ssss ssss ssss ssss ssss ssss ssss SWAP DROP DUP SWAP SWAP OVER DUP OVER OVER OVER inv shift DROP DUP OVER SWAP SWAP DROP DROP inv shift alu-op shift inv shift inv shift alu-op shift inv shift inv shift alu-op shift inv shift inv shift alu-op shift OPERATION
TABLE 19. STEP MATH FUNCTIONS (NOTE 25) INSTRUCTION CODE 15 14 13 12 1010 11 10 9 8 ---7654 - - -1 3210 ---(See the Programmer's Reference Manual) OPERATION
NOTE: 25. These instructions perform multi-step math functions such as multiplication, division and square root functions. Use of either the Streamed instruction mode or masking of interrupts is recommended to avoid erroneous results when performing Step Math operations. Unsigned Division: Load dividend into TOP and NEXT Load divisor into MD Execute single step form of D2 (Note 25) instruction 1 time Execute opcode A41A 1 time Execute opcode A45A 14 times Execute opcode A458 1 time The quotient is in NEXT , the remainder in TOP Square Root Operations: Load value into TOP and NEXT Load 8000H into SR Load 0 into MD Execute single step form of D2 (Note 25) instruction 1 time Execute opcode A51A 1 time Execute opcode A55A 14 times Execute opcode A558 1 time The root is in NEXT , the remainder in TOP
33
HS-RTX2010RH
TABLE 20. ALU LOGIC FUNCTIONS/OPCODES cccc 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 110 101 100 011 010 aaa 001 AND NOR SWAPSWAP-c OR NAND + +c XOR XNOR -c With Borrow With Carry With Borrow FUNCTION
TABLE 21. SHIFT FUNCTIONS STATUS OF C CY CY Z15 Z15 0 Z0 0 Z15 CY CY Z15 Z15 0 TN0 0 Z15
TOP REGISTER
T15 Z15 Z15 Z14 Z14 CY CY 0 Z15 Z15 Z15 Z14 Z14 CY CY 0 Z15 Tn Zn Z15 Zn-1 Zn-1 Zn+1 Zn+1 Zn+1 Zn+1 Zn Zn Zn-1 Zn-1 Zn+1 Zn+1 Zn+1 Zn+1 T0 Z0 Z15 0 CY Z1 Z1 Z1 Z1 Z0 Z0 TN15 TN15 Z1 Z1 Z1 Z1 N15
NEXT REGISTER
Nn TNn TNn TNn TNn TNn TNn TNn TNn TNn-1 TNn-1 TNn-1 TNn-1 TNn+1 TNn+1 TNn+1 TNn+1 N0 TN0 TN0 TN0 TN0 TN0 TN0 TN0 TN0 0 CY 0 CY TN1 TN1 TN1 TN1
SHIFT ssss 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100
NAME No Shift 0< 2* 2*c cU2/ c2/ U2/ 2/ N2* N2*c D2* D2*c cUD2/ Sign Extend
FUNCTION
TN15 TN15 TN15 TN15 TN15 TN15 TN15 TN15 TN14 TN14 TN14 TN14 Z0 Z0 Z0 Z0
Arithmetic Left Shift Rotate Left Right Shift Out of Carry Rotate Right Through Carry Logical Right Shift Arithmetic Right Shift Left Shift of NEXT Rotate NEXT Left 32-Bit Left Shift 32-Bit Rotate Left 32-Bit Right Shift Out of Carry 32-Bit Rotate Right Through Carry 32-Bit Logical Right Shift 32-Bit Right Shift
1101 (Note) cD2/ 1110 1111 UD2/ D2/
NOTE: See the Programmer's Reference Manual. Where: T15-Most significant bit of TOP Tn-Typical bit of TOP T0-Least significant bit of TOP N15-Most significant bit of NEXT Nn-Typical bit of NEXT N0-Least significant bit of NEXT C-Carry bit CY-Carry bit before operation Zn-ALU output Z15-Most significant bit 15 of ALU output TNn-Original value of typical bit of NEXT
34
HS-RTX2010RH
TABLE 22. MAC/BARREL SHIFTER/LZD INSTRUCTIONS INSTRUCTION CODE 15 14 13 12 1011 1011 1011 1011 1011 1011 1011 1011 1011 1011 1011 1011 1011 1011 1011 1011 1011 1011 1011 1011 1011 1011 11 10 9 8 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1110 1110 1110 1110 1110 1110 7654 00R0 00R0 00R0 00R0 00R0 00R0 00R1 00R1 10R1 00R1 10R1 10R1 00R1 00R1 00R1 00R1 00R1 00R1 00R1 10R1 10R1 10R1 321 0 1000 1001 1010 1100 1110 1111 0001 0010 0010 0011 0110 0111 0100 0101 0110 0111 0010 0110 0111 0010 0110 0111 Forth 0 = Double Shift Right Arithmetic Double Shift Right Logical Clear MAC Accumulator Double Shift Left Logical Floating Point Normalize Shift MAC Output Regs Right Streamed MAC Between Stack and Memory Streamed MAC Between ASIC Bus and Memory Mixed Mode Multiply Unsigned Multiply Signed Multiply Signed Multiply and Subtract from Accumulator Mixed Mode Multiply Accumulate Unsigned Multiply Accumulate Signed Multiply Accumulate Load MXR Register Load MLR Register Load MHR Register Store MXR Register Store MLR Register Store MHR Register OPERATION
35
HS-RTX2010RH Die Characteristics
DIE DIMENSIONS: 364 mils x 371 mils x 21 mils 1mil INTERFACE MATERIALS: Glassivation: Type: SiO2 Thickness: 8kA 1kA Top Metallization: Type: Al/Si/Cu Thickness: 7.5kA 2kA Substrate: TSOS5 CMOS, Silicon on Sapphire Backside Finish: Silicon ASSEMBLY RELATED INFORMATION: Substrate Potential: Unbiased (SOS) ADDITIONAL INFORMATION: Worst Case Current Density: 1.0 x 105 A/cm2
Metallization Mask Layout
(5) INTSUP
HS-RTX2010RH
(CQFP PIN 1) GA02
(82) MD15
(80) MD14
(79) MD13
(78) MD12
(76) MD10
(77) MD11
(11) EI5
(75) MD09
(84) GA01
(83) GA00
(81) GND
(2) TCLK
(6) VCC
(10) EI4
(4) NMI
(3) INTA
(9) EI3
(8) EI2
(7) EI1
RESET (12) WAIT (13) ICLK (14) GR/W (15) GIO (16) GD15 (17) GD14 (18) GD13 (19) GND (20) GD12 (21) GD11 (22) GD10 (23) GD09 (24) GD08 (25) GD07 (26) VCC (27) GD06 (28) GD05 (29) GD04 (30) GD03 (31) GND (32)
(74) MD08 (73) VCC (72) MD07 (71) MD06 (70) MD05 (69) GND (68) MD04 (67) MD03 (66) MD02 (65) MD01 (64) MD00 (63) MR/W (62) PCLK (61) BOOT (60) NEW (59) UDS (58) LDS (57) GND (56) MA19 (55) MA18 (54) MA17
MA01 (36)
MA02 (37)
MA03 (38)
MA04 (39)
MA05 (40)
MA06 (41)
MA07 (42)
MA08 (43)
MA09 (45)
MA10 (46)
MA11 (47)
MA12 (48)
MA13 (49)
MA14 (51)
MA15 (52)
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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MA16 (53)
GD02 (33)
GD01 (34)
GD00 (35)
GND (44)
VCC (50)

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